57 open listings · Page 1 of 3
Roles posted by organizations here, alongside roles we found on employers’ own careers sites. Crawled roles say so on the card and send you to the employer to apply. Only show organizations on Career App
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Design For Test Engineer IV (IC)
Arrow Electronics
Full-time · San Jose, CA · $112,200 – $170,500
This role involves implementing Design-For-Test strategies on advanced networking chips, including scan insertion, pattern generation, and memory built-in self-test verification. It's suited for an experienced test engineer comfortable with industry-standard DFT tools and semiconductor design flows.
Listed on Arrow Electronics’s careers site · Apply there ↗
FPGA Engineer
AeroVironment
Full-time · Albuquerque, NM · $88,500 – $135,000
This role involves designing and deploying firmware for space-based FPGA and embedded systems, working on high-reliability electronics for aerospace applications. It suits engineers with hardware description language experience who want to specialize in space technology and radiation-hardened system design.
Listed on AeroVironment’s careers site · Apply there ↗
Engineering Technician
Adtran
Adtran Huntsville HQ
A skilled technician supporting hardware and software engineers at a networking equipment company through assembly, testing, documentation, and design verification work. This role suits someone with electronics training and hands-on lab experience who can work independently across multiple engineering disciplines.
Microsoft WordFile Transfer Protocol (FTP)VoIP SystemsHTMLDynamic Host Configuration Protocol (DHCP)Power Platform CLI
Listed on Adtran’s careers site · Apply there ↗
Senior ASIC Design Engineer - DFX
NVIDIA
Santa Clara, CA · $168,000 – $310,500
NVIDIA is hiring a senior engineer to architect and implement design-for-test solutions for their next-generation AI chips, working across the full silicon lifecycle from design through post-silicon validation. This role suits someone with deep DFT expertise and SoC design experience who enjoys mentoring others and collaborating across hardware and software teams.
Listed on NVIDIA’s careers site · Apply there ↗
SOC IP RTL Development Engineer
Samsung Semiconductor
This role involves designing high-speed serial interface IP blocks at the RTL level for Samsung's semiconductor products, requiring deep expertise in protocols like USB, PCIe, and Ethernet. It suits mid-to-senior engineers with 8-11 years of experience who have shipped silicon and can mentor others while working across cross-functional teams.
Listed on Samsung Semiconductor’s careers site · Apply there ↗
Senior Formal Verification Engineer – AI SoC Development
Intel
Full-time · $220,920 – $311,890
This role leads formal verification strategy for Intel's AI chip designs, ensuring correctness through advanced formal methods and SystemVerilog assertions. It suits senior engineers with deep expertise in formal verification methodologies who can mentor others and drive sign-off on complex SoC blocks.
Listed on Intel’s careers site · Apply there ↗
New College Grad - Mixed Signal Design Engineer, HBM
Micron Technology
2 locations
This role leads the physical design of Micron's high-bandwidth memory chips from initial schematic through final manufacturing data, owning placement, routing, timing closure, and power delivery across advanced process nodes. It suits experienced IC designers comfortable driving complex multi-team efforts in memory-centric designs and learning HBM-specific architecture if not already expert in it.
Listed on Micron Technology’s careers site · Apply there ↗
Choose a location to apply
Design Engineer
Broadcom Inc.
Full-time · Fort Collins, CO · $60,200 – $96,300
Join Broadcom's ASIC design team to work on physical implementation of high-performance custom silicon for AI and networking products, gaining hands-on experience with advanced process nodes and modern design tools. This role suits engineers with VLSI fundamentals who want exposure to the complete chip design cycle in a collaborative, learning-focused environment.
Listed on Broadcom Inc.’s careers site · Apply there ↗
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Physical Design Engineer
Ambarella
US Headquarters · $140,000 – $156,000
This role involves designing and optimizing the physical layout of advanced AI processor chips, from initial floorplanning through final verification and tape-out. It suits engineers with several years of experience in digital chip design who want to work on cutting-edge low-power SoCs using industry-standard tools.
Listed on Ambarella’s careers site · Apply there ↗
Apply for FPGA Engineer at Astranis on their site
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FPGA Engineer
Astranis
San Francisco, CA · $140,000 – $205,000
This role designs and verifies the FPGA logic that powers Astranis's satellite communications systems, working across radio, avionics, and ground infrastructure. It suits engineers with RTL experience who want to contribute to space technology at a company building production satellites.
Listed on Astranis’s careers site · Apply there ↗
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Design Verification Engineer
Baidu
Sunnyvale, CA
This role verifies the functionality of AI accelerator chips at Baidu's Sunnyvale office, requiring someone with deep UVM and SystemVerilog expertise to develop testbenches, run simulations, and close coverage across block and system levels. It suits experienced verification engineers who want to work on cutting-edge AI silicon and thrive in a fast-paced technical environment.
Listed on Baidu’s careers site · Apply there ↗
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ASIC Design Engineer (eInfochips)
Arrow Electronics
Full-time
This role involves designing and verifying digital circuits using Verilog and industry-standard EDA tools, with particular emphasis on high-speed interfaces and low-power design techniques. It suits experienced hardware engineers who are comfortable with scripting and customer communication in a consultant-style environment.
Listed on Arrow Electronics’s careers site · Apply there ↗
Physical Verification and EMIR Signoff Lead
Samsung Semiconductor
This role leads physical verification and electrical analysis for advanced semiconductor chip designs at Samsung's major R&D center in India, overseeing signoff activities across multiple verification domains. It suits experienced chip designers who have worked on cutting-edge process nodes and can mentor junior engineers while driving process improvements.
Listed on Samsung Semiconductor’s careers site · Apply there ↗
Senior Circuit Design Engineer - Noise
NVIDIA
$168,000 – $264,500
Senior circuit design engineer focusing on noise mitigation and analog/mixed-signal circuit design for NVIDIA's next-generation processors. Suited for experienced EE professionals who excel at deep submicron design, SPICE simulation, and cross-functional collaboration on high-reliability silicon.
Monte Carlo SimulationDigital Circuit DesignStatic Timing AnalysisAnalog Circuit DesignMake (Integromat)Perl
Listed on NVIDIA’s careers site · Apply there ↗
Director, SoC Design Engineering
Intel
Full-time · $220,920 – $311,890
Lead functional verification strategy and execution for Intel's advanced system-on-chip designs, mentoring engineers while driving innovation across simulation, emulation, and formal verification methodologies. This role suits experienced verification engineers ready to influence Intel's technical direction and shape product quality at scale.
Listed on Intel’s careers site · Apply there ↗
Lead ASIC Design Engineer
Broadcom Inc.
Full-time · San Jose, CA · $143,800 – $230,000
This role leads the digital design of next-generation chips from architecture through tape-out, requiring deep expertise in RTL, synthesis, timing, and cross-team coordination. It suits experienced ASIC engineers ready to own a complete silicon project as the primary technical authority.
Listed on Broadcom Inc.’s careers site · Apply there ↗
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FPGA Engineer Engineer (eInfochips)
Arrow Electronics
Full-time
This is a senior FPGA design role requiring nearly a decade of experience with digital logic, EDA tools, and high-speed protocols like PCIe and AXI. The position suits someone with deep expertise in RTL design, timing analysis, and low-power design techniques who can work on-site at a semiconductor services company.
Listed on Arrow Electronics’s careers site · Apply there ↗
STA Lead Engineer
Samsung Semiconductor
Lead a team of STA engineers in semiconductor design, taking ownership of timing closure, synthesis, and physical design optimization for advanced chips. This role suits experienced ASIC design professionals who excel at both technical execution and mentoring, with deep expertise in constraints, low-power design, and high-speed timing closure.
Listed on Samsung Semiconductor’s careers site · Apply there ↗
Senior VLSI Integration Engineer
NVIDIA
NVIDIA seeks a Senior ASIC engineer to lead chip-level design integration across their System-On-Chip group, collaborating with multiple teams on complex networking chip architecture, design automation, and quality optimization. This role suits experienced RTL designers passionate about SOC design methodologies and solving structural challenges in advanced chip design.
Listed on NVIDIA’s careers site · Apply there ↗
CPU RTL Design Engineer
Intel
Full-time · $141,910 – $269,100
Intel is seeking an experienced engineer to design and optimize the logic for their next-generation CPU processors, writing RTL code and managing the simulation and verification of processor architectures. This role suits someone with 5+ years of RTL design experience who wants to work on cutting-edge processor technology at a company scale.
Listed on Intel’s careers site · Apply there ↗
ASIC Implementation Engineer
Broadcom Inc.
3 locations · $143,800 – $230,000
Broadcom seeks a Physical Design Engineer to lead chip floorplanning and physical implementation from RTL through silicon tape-out, focusing on next-generation AI and PCIe Switch products. This role suits senior engineers with deep expertise in top-level floorplanning, clock trees, and cross-functional coordination across design, package, and methodology teams.
Listed on Broadcom Inc.’s careers site · Apply there ↗
Choose a location to apply
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Senior Design Verification Engineer (eInfochips Inc)
Arrow Electronics
Full-time · US-MN-Minnesota (Remote Employees)
This role involves designing and building verification environments for semiconductor products using industry-standard methodologies and tools. It suits experienced engineers who excel at test automation and debugging complex hardware systems at the subsystem and system level.
Listed on Arrow Electronics’s careers site · Apply there ↗
NAND BM IP DV Engineer
Samsung Semiconductor
Samsung is seeking a design verification engineer to build and enhance test environments for memory semiconductor products, working with industry-standard verification methodologies. This role suits experienced engineers who are comfortable debugging complex systems independently while collaborating closely with design teams.
Listed on Samsung Semiconductor’s careers site · Apply there ↗
Senior Power Integrity Methodology CAD Engineer
NVIDIA
Full-time · $168,000 – $310,500
NVIDIA seeks a senior engineer to develop power integrity analysis methodologies and workflows for their GPU chip design process, including IR analysis, EMIR signoff, and tool automation. This role suits someone with deep expertise in electrical engineering methodology who enjoys solving complex technical problems across large hardware teams.
Listed on NVIDIA’s careers site · Apply there ↗
Sr. EDA Tools Engineer - PERC ESD
Intel
Full-time · Hillsboro, OR · $149,600 – $284,580
This role develops electrostatic discharge verification rule sets and methodologies for Intel's most advanced semiconductor process technologies, enabling design teams to deliver products faster. It suits engineers with strong physical design verification backgrounds who want to solve complex reliability challenges at the cutting edge of semiconductor manufacturing.
Listed on Intel’s careers site · Apply there ↗