Skill
Static Timing Analysis
Engineering (Mechanical, Electrical, Civil and Environmental)
Static Timing Analysis (STA) is a method used in digital integrated circuit design to verify that a chip's timing constraints are met without requiring dynamic simulation of all possible input patterns. It is performed by hardware and ASIC/FPGA design engineers using tools like Synopsys PrimeTime to check for setup and hold time violations across all paths in a circuit. STA is a critical step in the chip design sign-off process to ensure a design will function correctly at its target clock speed.
Static Timing Analysis in the job market
Last checked October 28, 2026
- Open roles
- 17
- Employers
- 7
- Median pay
- —
- Disclose pay
- —
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Open roles requiring Static Timing Analysis (17)
NVIDIA 2027 Internships: Hardware ASIC Design
NVIDIA
Internship · Santa Clara, CA · $20 – $71 / hour
NVIDIA is hiring interns for a 12-week full-time program focused on hardware ASIC design, where you'll contribute to real projects spanning chip architecture, physical design, and verification. The role suits students pursuing degrees in electrical or computer engineering who want hands-on experience with cutting-edge hardware development tools and methodologies.
Listed on NVIDIA’s careers site · Apply there ↗
ASIC / FPGA Digital Design Engineer – (Associate or Experienced)
Boeing
Full-time · $98,600 – $133,400
Boeing is seeking digital design engineers to develop ASICs, FPGAs, and mixed-signal systems for aerospace and defense programs including satellites, aircraft, and autonomous systems. The role spans requirements, HDL development, simulation, synthesis, timing analysis, and integration work, with opportunities to grow from focused technical contributors into broader subsystem ownership and leadership.
Listed on Boeing’s careers site · Apply there ↗
Physical Design Engineer II (eInfochips Inc)
Arrow Electronics
Full-time · San Jose, CA
This role executes the physical design and place-and-route phases of ASIC chip development, collaborating with RTL and architecture teams to meet timing and power targets through the full implementation flow. It suits engineers with 7+ years of hands-on EDA tool experience who want to work on advanced-node chip design at scale.
Listed on Arrow Electronics’s careers site · Apply there ↗
Sr. Staff Physical Design PPA Engineer
Samsung Semiconductor
Full-time · Austin, TX · $180,200 – $270,400
Samsung seeks a senior physical design engineer to lead power, performance, and area optimization initiatives across their GPU and custom semiconductor IP. This role suits experienced design implementation professionals who excel at problem-solving, understand chip design flows deeply, and can drive methodology improvements across synthesis, place-and-route, and signoff.
Listed on Samsung Semiconductor’s careers site · Apply there ↗
EDA Tools Hardware Engineer
Intel
Full-time · $141,910 – $269,100
Intel is hiring a hardware engineer to develop full-chip physical design implementation flows, including placement, routing, clock synthesis, and power grid planning for advanced semiconductor designs. This role suits experienced engineers with a background in physical design and knowledge of EDA tools like Innovus.
Listed on Intel’s careers site · Apply there ↗
Principal Compute Pathfinding ASIC Design
Micron Technology
Full-time · $164,000 – $358,000
This role leads ASIC architecture and pathfinding work at Micron, focusing on defining next-generation compute designs 3–5 years ahead of product launch. It suits experienced chip architects who can bridge system-level strategy with RTL implementation and work across cross-functional teams to drive technical roadmaps.
Listed on Micron Technology’s careers site · Apply there ↗
CPU Digital Design Engineer
Baidu
Sunnyvale, CA
This role involves designing efficient CPU controllers for 5G cellular modems, working on microarchitecture and RTL implementation with international teams at advanced process nodes. It suits engineers with hands-on experience in CPU architecture and digital design who want to ship high-performance, power-efficient processors.
Listed on Baidu’s careers site · Apply there ↗
Physical Design Engineer (Einfochips Inc)
Arrow Electronics
Full-time · $87,400 – $165,000
A physical design engineer needed to execute synthesis, place-and-route, and timing analysis for ASIC chip partitions while collaborating with architects and RTL designers to resolve implementation challenges. This role suits engineers with deep expertise in EDA tools and advanced node technologies who can manage tight schedules and drive design convergence.
Listed on Arrow Electronics’s careers site · Apply there ↗
Senior ASIC Design Engineer - DFT
NVIDIA
Santa Clara, CA · $168,000 – $310,500
NVIDIA is hiring a senior engineer to architect and implement design-for-test solutions for their next-generation AI chips, working across the full silicon lifecycle from design through post-silicon validation. This role suits someone with deep DFT expertise and SoC design experience who enjoys mentoring others and collaborating across hardware and software teams.
Listed on NVIDIA’s careers site · Apply there ↗
Design Technology Co-Optimization (DTCO) Engineer, Design flow and Methodology
Samsung Semiconductor
Full-time · Austin, TX · $180,200 – $270,400
Samsung is seeking a highly experienced engineer to develop design and analysis flows for their advanced semiconductor technology, optimizing the interplay between process technology and chip design methodology. This role suits someone with deep expertise in CAD tools, digital design flows, and a track record of solving complex engineering challenges in high-performance computing.
Listed on Samsung Semiconductor’s careers site · Apply there ↗
Asked for alongside Static Timing Analysis
Measured from the 17 open roles that name Static Timing Analysis — not from a curated list.
- Tcl10 roles58.8%
- Python8 roles47.1%
- Perl7 roles41.2%
- Physical Design4 roles23.5%
- Verilog4 roles23.5%
- C++3 roles17.6%
- Clock Tree Synthesis3 roles17.6%
Roles that use Static Timing Analysis
Employers hiring for Static Timing Analysis
7 in total, most open roles first.
- NVIDIA8 roles
- AEArrow Electronics2 roles
- Intel2 roles
- Samsung Semiconductor2 roles
- BBaidu1 role
- BBoeing1 role
Related skills
Curated neighbors in the taxonomy, whether or not employers ask for them together.