Skill
Static Timing Analysis
Engineering (Mechanical, Electrical, Civil and Environmental)
Static Timing Analysis (STA) is a method used in digital integrated circuit design to verify that a chip's timing constraints are met without requiring dynamic simulation of all possible input patterns. It is performed by hardware and ASIC/FPGA design engineers using tools like Synopsys PrimeTime to check for setup and hold time violations across all paths in a circuit. STA is a critical step in the chip design sign-off process to ensure a design will function correctly at its target clock speed.
Static Timing Analysis in the job market
Last checked September 13, 2026
- Open roles
- 20
- Employers
- 6
- Median pay
- —
- Disclose pay
- —
on Career App right now
hiring for it
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Open roles requiring Static Timing Analysis (20)
ASIC Design Engineer (eInfochips)
Arrow Electronics
Full-time
This role involves designing and verifying digital circuits using Verilog and industry-standard EDA tools, with particular emphasis on high-speed interfaces and low-power design techniques. It suits experienced hardware engineers who are comfortable with scripting and customer communication in a consultant-style environment.
Listed on Arrow Electronics’s careers site · Apply there ↗
Senior ASIC Design Engineer - DFX
NVIDIA
Santa Clara, CA · $168,000 – $310,500
NVIDIA is hiring a senior engineer to architect and implement design-for-test solutions for their next-generation AI chips, working across the full silicon lifecycle from design through post-silicon validation. This role suits someone with deep DFT expertise and SoC design experience who enjoys mentoring others and collaborating across hardware and software teams.
Listed on NVIDIA’s careers site · Apply there ↗
STA Lead Engineer
Samsung Semiconductor
Lead a team of STA engineers in semiconductor design, taking ownership of timing closure, synthesis, and physical design optimization for advanced chips. This role suits experienced ASIC design professionals who excel at both technical execution and mentoring, with deep expertise in constraints, low-power design, and high-speed timing closure.
Listed on Samsung Semiconductor’s careers site · Apply there ↗
Director, Silicon Design Engineering
Intel
Full-time · $220,920 – $311,890
A Physical Design Timing Engineer role focused on analyzing and optimizing timing, power, and performance for Intel's next-generation System-on-Chip products. This position suits experienced engineers with deep expertise in static timing analysis, SoC clocking, and cross-functional collaboration who want to shape the future of semiconductor design.
Listed on Intel’s careers site · Apply there ↗
ASIC Implementation Engineer STA
Broadcom Inc.
Full-time · San Jose, CA · $143,800 – $230,000
This role leads static timing analysis and closure for ASIC designs, ensuring they meet performance targets across manufacturing and environmental variations. It suits engineers with deep expertise in timing constraints, sign-off tools, and automation who can drive complex multi-scenario analysis from RTL through physical design.
Listed on Broadcom Inc.’s careers site · Apply there ↗
CPU Digital Design Engineer
Baidu
Sunnyvale, CA
This role involves designing efficient CPU controllers for 5G cellular modems, working on microarchitecture and RTL implementation with international teams at advanced process nodes. It suits engineers with hands-on experience in CPU architecture and digital design who want to ship high-performance, power-efficient processors.
Listed on Baidu’s careers site · Apply there ↗
FPGA Engineer Engineer (eInfochips)
Arrow Electronics
Full-time
This is a senior FPGA design role requiring nearly a decade of experience with digital logic, EDA tools, and high-speed protocols like PCIe and AXI. The position suits someone with deep expertise in RTL design, timing analysis, and low-power design techniques who can work on-site at a semiconductor services company.
Listed on Arrow Electronics’s careers site · Apply there ↗
Senior Circuit Design Engineer - Noise
NVIDIA
$168,000 – $264,500
Senior circuit design engineer focusing on noise mitigation and analog/mixed-signal circuit design for NVIDIA's next-generation processors. Suited for experienced EE professionals who excel at deep submicron design, SPICE simulation, and cross-functional collaboration on high-reliability silicon.
Listed on NVIDIA’s careers site · Apply there ↗
Senior Staff Engineer, Physical Implementation CAD Lead
Samsung Semiconductor
Full-time · $180,200 – $297,200
Samsung is seeking a senior engineer to lead physical design CAD methodology development for GPU and SoC chips at advanced technology nodes. This role suits an expert in place-and-route tools and sub-5nm design challenges who can drive automation, mentor teams, and collaborate across EDA vendors and internal design groups.
Listed on Samsung Semiconductor’s careers site · Apply there ↗
Senior Physical Design Engineer (CPU)
Intel
Full-time · Hillsboro, OR · $141,910 – $269,100
This role involves owning the physical design and implementation of CPU core blocks, executing the full RTL-to-GDS flow including synthesis, place-and-route, and timing closure. It suits experienced hardware engineers with deep expertise in digital design tools and a track record of shipping complex silicon at advanced process nodes.
Listed on Intel’s careers site · Apply there ↗
Asked for alongside Static Timing Analysis
Measured from the 20 open roles that name Static Timing Analysis — not from a curated list.
- Tcl17 roles85.0%
- Perl12 roles60.0%
- Python11 roles55.0%
- Cadence OrCAD/Allegro5 roles25.0%
- Verilog5 roles25.0%
- Clock Tree Synthesis3 roles15.0%
- SystemVerilog3 roles15.0%
Roles that use Static Timing Analysis
Employers hiring for Static Timing Analysis
6 in total, most open roles first.
- NVIDIA6 roles
- AEArrow Electronics4 roles
- Samsung Semiconductor4 roles
- Intel3 roles
- Broadcom Inc.2 roles
- BBaidu1 role
Related skills
Curated neighbors in the taxonomy, whether or not employers ask for them together.