AE
$112,200 – $170,500
Listed on Arrow Electronics’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
This role involves implementing Design-For-Test strategies on advanced networking chips, including scan insertion, pattern generation, and memory built-in self-test verification. It's suited for an experienced test engineer comfortable with industry-standard DFT tools and semiconductor design flows.
Our summary, not Arrow Electronics’s wording. The full posting is on their site.
What they ask for
Required
- 5–7 years of DFT experience
- Scan insertion, ATPG, and pattern simulation expertise
- MBIST insertion and verification
- IEEE 1149.1 JTAG insertion and verification
- Scripting in Perl, Shell, or TCL
- Experience with multi-million gate count SoCs in networking or consumer domains
- Mentor Tessent proficiency
- Bachelor's degree in Microelectronics or Electronics
Nice to have
- Low power DFT experience
- Familiarity with PLL and Serdes IP blocks