Skill
Vivado
Engineering (Mechanical, Electrical, Civil and Environmental)
Vivado is a design suite from AMD (formerly Xilinx) used to synthesize, simulate, and implement designs for FPGAs and programmable SoCs. Hardware and digital logic engineers use it to write and debug HDL code (Verilog/VHDL), run timing analysis, and generate bitstreams for programming Xilinx FPGA chips. It replaced Xilinx's older ISE toolchain and supports high-level synthesis from C/C++ as well.
Open roles requiring Vivado (1)
FPGA Engineer
Astranis
San Francisco, CA · $140,000 – $205,000
This role designs and verifies the FPGA logic that powers Astranis's satellite communications systems, working across radio, avionics, and ground infrastructure. It suits engineers with RTL experience who want to contribute to space technology at a company building production satellites.
Listed on Astranis’s careers site · Apply there ↗