$20 – $71 / hour
Listed on NVIDIA’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
NVIDIA is seeking graduate students to work on hardware design for test infrastructure over a 12-week internship, contributing to chip validation and debugging on their accelerated computing platforms. This role suits ambitious engineers interested in semiconductor testing, timing analysis, and design automation within a leading AI hardware company.
Our summary, not NVIDIA’s wording. The full posting is on their site.
Skills this role names
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What they ask for
Required
- Currently enrolled in M.S. or Ph.D. program in Electrical Engineering, Computer Engineering, or related field
- Anticipated graduation date clearly listed on resume or CV
- Course or internship experience in Design for Test (DFT), Digital Design, Test Architecture and DFT Planning, or Static Timing Analysis (STA)
Nice to have
- Experience with Pre-Silicon and Post-Silicon issue debugging
- Knowledge of Scan Chain Design and ATPG
- Experience with Boundary Scan and JTAG
- Memory BIST (Built-In Self-Test) experience
- Logic BIST and compression techniques (EDT, Streaming Scan Network)
- At-Speed and Delay Testing experience
- Perl, TCL, C, C++, or Python programming experience
- Familiarity with Synopsys, TetraMAX, or Cadence Modus tools
- Linux experience