Listed on Broadcom Inc.’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
This role develops behavioral models of analog circuit blocks in SystemVerilog for chip verification, bridging the analog design and digital verification teams. It suits engineers with strong analog circuit knowledge who can code detailed mixed-signal simulations and validate them against schematics.
Our summary, not Broadcom Inc.’s wording. The full posting is on their site.
Skills this role names
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What they ask for
Required
- 8+ years of related experience
- SystemVerilog DMS modeling of analog IPs
- Understanding of Verilog-AMS modeling language
- Knowledge of SystemVerilog UDT/UDR nettype
- Familiarity with analog circuits: LDOs, TIAs, analog muxing, SARADC, comparators, DACs, buffers, amplifiers
- RTL coding for digital logic and testbench creation
- SV vs. schematic verification capability
- Experience with Cadence simulation and linting tools
- Scripting in TCL, Perl, or Python
Nice to have
- Experience using AI tools such as Cursor or chipAgents for model generation
- Familiarity with analog schematic editors