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Listed on Baidu’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
This role verifies the functionality of AI accelerator chips at Baidu's Sunnyvale office, requiring someone with deep UVM and SystemVerilog expertise to develop testbenches, run simulations, and close coverage across block and system levels. It suits experienced verification engineers who want to work on cutting-edge AI silicon and thrive in a fast-paced technical environment.
Our summary, not Baidu’s wording. The full posting is on their site.
Skills this role names
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What they ask for
Required
- Minimum 5 years of UVM-based verification experience on complex projects
- Advanced knowledge of ASIC design and verification flows
- Advanced SystemVerilog and UVM methodology expertise
- Proficiency in constrained random testing, coverage closure, and gate-level simulation
- Experience with at least one high-speed interface (PCIe, Ethernet, HBM, GDDR, DDR, MMU, Cache)
- Fluency in English and Chinese
Nice to have
- Scripting language experience (Perl, Python, Tcl)
- C/C++ familiarity
- Formal verification experience (Model Checking, Equivalence Checking)
- Mixed-signal co-simulation and emulation experience