A
$140,000 – $156,000
Listed on Ambarella’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
This role involves designing and optimizing the physical layout of advanced AI processor chips, from initial floorplanning through final verification and tape-out. It suits engineers with several years of experience in digital chip design who want to work on cutting-edge low-power SoCs using industry-standard tools.
Our summary, not Ambarella’s wording. The full posting is on their site.
Skills this role names
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What they ask for
Required
- BS/MS in EE or computer science, or equivalent experience
- 3–5+ years of VLSI digital design and layout experience
- Good understanding of VLSI digital design, layout, and timing closure
- Basic knowledge of circuit design, device delays, and timing at gate level
- Proficiency with Cadence Innovus/Quantus/Tempus, Synopsys Fusion Compiler/ICC2/StarRC/Primetime, or Mentor Calibre
- Programming and scripting in Perl, Python, TCL, C-shell, or make
- Knowledge of Verilog or VHDL
- Self-motivated with strong communication skills
Nice to have
- Experience with Cadence Innovus/Genus/Conformal and Synopsys Primetime/StarRC
- Deep understanding of hierarchical physical design strategies and nanometer technology issues
- Hands-on STA experience with multi-mode multi-corner analysis
- Track record of delivering tape-out quality GDSII with silicon success in sub-10 nm nodes