$180,200 – $270,400
Listed on Samsung Semiconductor’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
Samsung seeks a senior physical design engineer to lead power, performance, and area optimization initiatives across their GPU and custom semiconductor IP. This role suits experienced design implementation professionals who excel at problem-solving, understand chip design flows deeply, and can drive methodology improvements across synthesis, place-and-route, and signoff.
Our summary, not Samsung Semiconductor’s wording. The full posting is on their site.
Skills this role names
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What they ask for
Required
- 10+ years experience with Bachelor's in Computer Science/Computer Engineering or equivalent, OR 8+ years with Master's degree, OR 6+ years with PhD
- Understanding of SOC/ASIC design flow with tapeout experience
- Experience with synthesis, block, and full chip implementation using industry P&R and STA tools
- Block-level floor planning and power grid implementation
- Area and congestion optimization
- TCL, Perl, Shell, and/or Python scripting
- Electrical Engineering fundamentals knowledge
- Attention to detail and communication skills
Nice to have
- 7nm FinFET or smaller process node experience
- Hands-on clock tree synthesis experience
- Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure