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NVIDIA

Internship · Santa Clara, CA · $20 – $71 / hour

NVIDIA is hiring interns for a 12-week hardware verification program where you'll work on projects validating GPUs and processors using industry tools and methodologies. This suits students pursuing electrical or computer engineering degrees who want hands-on experience with verification workflows in accelerated computing.

Listed on NVIDIA’s careers site · Apply there ↗

FLIR Systems

Goleta, CA · $113,600 – $151,400

Teledyne seeks an experienced layout engineer to design the semiconductor layouts for infrared imaging chips used in defense, medical, and scientific applications. You'll work with analog and digital design teams to translate schematics into high-performance integrated circuits, managing signal integrity and manufacturing constraints from concept through production.

Listed on FLIR Systems’s careers site · Apply there ↗

Arrow Electronics

Full-time · San Jose, CA · $112,200 – $170,500

This role involves implementing Design-For-Test strategies on advanced networking chips, including scan insertion, pattern generation, and memory built-in self-test verification. It's suited for an experienced test engineer comfortable with industry-standard DFT tools and semiconductor design flows.

Listed on Arrow Electronics’s careers site · Apply there ↗

AeroVironment

Full-time · Albuquerque, NM · $88,500 – $135,000

This role involves designing and deploying firmware for space-based FPGA and embedded systems, working on high-reliability electronics for aerospace applications. It suits engineers with hardware description language experience who want to specialize in space technology and radiation-hardened system design.

Listed on AeroVironment’s careers site · Apply there ↗

Adtran

Adtran Huntsville HQ

A skilled technician supporting hardware and software engineers at a networking equipment company through assembly, testing, documentation, and design verification work. This role suits someone with electronics training and hands-on lab experience who can work independently across multiple engineering disciplines.

Listed on Adtran’s careers site · Apply there ↗

Samsung Semiconductor

Samsung is seeking a design verification engineer to build and enhance test environments for memory semiconductor products, working with industry-standard verification methodologies. This role suits experienced engineers who are comfortable debugging complex systems independently while collaborating closely with design teams.

Listed on Samsung Semiconductor’s careers site · Apply there ↗

Intel

Full-time · $220,920 – $311,890

This role leads formal verification strategy for Intel's AI chip designs, ensuring correctness through advanced formal methods and SystemVerilog assertions. It suits senior engineers with deep expertise in formal verification methodologies who can mentor others and drive sign-off on complex SoC blocks.

Listed on Intel’s careers site · Apply there ↗

Micron Technology

Full-time · Boise, ID

This role involves analyzing failures in high-bandwidth memory products through electrical and physical testing techniques to identify manufacturing root causes and support production ramp. It suits recent graduates in engineering or materials science who want to launch a career in semiconductor yield engineering with hands-on experience in fault isolation and process improvement.

Listed on Micron Technology’s careers site · Apply there ↗

Broadcom Inc.

Full-time · Fort Collins, CO · $60,200 – $96,300

Join Broadcom's ASIC design team to work on physical implementation of high-performance custom silicon for AI and networking products, gaining hands-on experience with advanced process nodes and modern design tools. This role suits engineers with VLSI fundamentals who want exposure to the complete chip design cycle in a collaborative, learning-focused environment.

Listed on Broadcom Inc.’s careers site · Apply there ↗

Ambarella

US Headquarters · $140,000 – $156,000

This role involves designing and optimizing the physical layout of advanced AI processor chips, from initial floorplanning through final verification and tape-out. It suits engineers with several years of experience in digital chip design who want to work on cutting-edge low-power SoCs using industry-standard tools.

Listed on Ambarella’s careers site · Apply there ↗