20 open listings
Roles posted by organizations here, alongside roles we found on employers’ own careers sites. Crawled roles say so on the card and send you to the employer to apply. Only show organizations on Career App
AE
ASIC Design Engineer (eInfochips)
Arrow Electronics
Full-time
This role involves designing and verifying digital circuits using Verilog and industry-standard EDA tools, with particular emphasis on high-speed interfaces and low-power design techniques. It suits experienced hardware engineers who are comfortable with scripting and customer communication in a consultant-style environment.
Listed on Arrow Electronics’s careers site · Apply there ↗
Senior ASIC Design Engineer - DFX
NVIDIA
Santa Clara, CA · $168,000 – $310,500
NVIDIA is hiring a senior engineer to architect and implement design-for-test solutions for their next-generation AI chips, working across the full silicon lifecycle from design through post-silicon validation. This role suits someone with deep DFT expertise and SoC design experience who enjoys mentoring others and collaborating across hardware and software teams.
Listed on NVIDIA’s careers site · Apply there ↗
STA Lead Engineer
Samsung Semiconductor
Lead a team of STA engineers in semiconductor design, taking ownership of timing closure, synthesis, and physical design optimization for advanced chips. This role suits experienced ASIC design professionals who excel at both technical execution and mentoring, with deep expertise in constraints, low-power design, and high-speed timing closure.
Listed on Samsung Semiconductor’s careers site · Apply there ↗
Director, Silicon Design Engineering
Intel
Full-time · $220,920 – $311,890
A Physical Design Timing Engineer role focused on analyzing and optimizing timing, power, and performance for Intel's next-generation System-on-Chip products. This position suits experienced engineers with deep expertise in static timing analysis, SoC clocking, and cross-functional collaboration who want to shape the future of semiconductor design.
Listed on Intel’s careers site · Apply there ↗
ASIC Implementation Engineer STA
Broadcom Inc.
Full-time · San Jose, CA · $143,800 – $230,000
This role leads static timing analysis and closure for ASIC designs, ensuring they meet performance targets across manufacturing and environmental variations. It suits engineers with deep expertise in timing constraints, sign-off tools, and automation who can drive complex multi-scenario analysis from RTL through physical design.
Listed on Broadcom Inc.’s careers site · Apply there ↗
B
CPU Digital Design Engineer
Baidu
Sunnyvale, CA
This role involves designing efficient CPU controllers for 5G cellular modems, working on microarchitecture and RTL implementation with international teams at advanced process nodes. It suits engineers with hands-on experience in CPU architecture and digital design who want to ship high-performance, power-efficient processors.
Listed on Baidu’s careers site · Apply there ↗
AE
FPGA Engineer Engineer (eInfochips)
Arrow Electronics
Full-time
This is a senior FPGA design role requiring nearly a decade of experience with digital logic, EDA tools, and high-speed protocols like PCIe and AXI. The position suits someone with deep expertise in RTL design, timing analysis, and low-power design techniques who can work on-site at a semiconductor services company.
Listed on Arrow Electronics’s careers site · Apply there ↗
Senior Circuit Design Engineer - Noise
NVIDIA
$168,000 – $264,500
Senior circuit design engineer focusing on noise mitigation and analog/mixed-signal circuit design for NVIDIA's next-generation processors. Suited for experienced EE professionals who excel at deep submicron design, SPICE simulation, and cross-functional collaboration on high-reliability silicon.
Monte Carlo SimulationDigital Circuit DesignStatic Timing AnalysisAnalog Circuit DesignMake (Integromat)Perl
Listed on NVIDIA’s careers site · Apply there ↗
Senior Staff Engineer, Physical Implementation CAD Lead
Samsung Semiconductor
Full-time · $180,200 – $297,200
Samsung is seeking a senior engineer to lead physical design CAD methodology development for GPU and SoC chips at advanced technology nodes. This role suits an expert in place-and-route tools and sub-5nm design challenges who can drive automation, mentor teams, and collaborate across EDA vendors and internal design groups.
Listed on Samsung Semiconductor’s careers site · Apply there ↗
Senior Physical Design Engineer (CPU)
Intel
Full-time · Hillsboro, OR · $141,910 – $269,100
This role involves owning the physical design and implementation of CPU core blocks, executing the full RTL-to-GDS flow including synthesis, place-and-route, and timing closure. It suits experienced hardware engineers with deep expertise in digital design tools and a track record of shipping complex silicon at advanced process nodes.
Listed on Intel’s careers site · Apply there ↗
STA Engineer
Broadcom Inc.
Fort Collins, CO · $129,400 – $207,000
Broadcom's ASIC Products Division seeks an experienced engineer to lead timing closure and analysis for high-performance chip designs, working across design and physical implementation teams. This role suits someone with deep expertise in static timing analysis and a track record managing complex timing challenges in advanced semiconductor technologies.
Listed on Broadcom Inc.’s careers site · Apply there ↗
AE
Physical Design Engineer II (eInfochips Inc)
Arrow Electronics
Full-time · San Jose, CA
This role executes the physical design and place-and-route phases of ASIC chip development, collaborating with RTL and architecture teams to meet timing and power targets through the full implementation flow. It suits engineers with 7+ years of hands-on EDA tool experience who want to work on advanced-node chip design at scale.
Listed on Arrow Electronics’s careers site · Apply there ↗
Senior Speed Characterization Engineer - Silicon Co-Design Group
NVIDIA
Full-time · Santa Clara, CA · $136,000 – $264,500
This role owns silicon speed characterization and validation for NVIDIA's AI processors, from first power-on through production. You'll close the gap between pre-silicon predictions and measured silicon performance, trace frequency failures to their root cause, build AI-driven test automation, and provide the data that settles architectural tradeoffs across the company.
Listed on NVIDIA’s careers site · Apply there ↗
Sr. Staff Physical Design PPA Engineer
Samsung Semiconductor
Full-time · Austin, TX · $180,200 – $270,400
Samsung seeks a senior physical design engineer to lead power, performance, and area optimization initiatives across their GPU and custom semiconductor IP. This role suits experienced design implementation professionals who excel at problem-solving, understand chip design flows deeply, and can drive methodology improvements across synthesis, place-and-route, and signoff.
Listed on Samsung Semiconductor’s careers site · Apply there ↗
CPU Physical Design Engineer
Intel
Full-time · 3 locations · $141,910 – $269,100
This role involves taking CPU designs from logic to manufacturing-ready layouts, managing the full physical design flow including timing, power delivery, and verification. It suits experienced hardware design engineers with deep expertise in EDA tools and processor architecture who want to work on Intel's leading-edge processor lines.
Listed on Intel’s careers site · Apply there ↗
Choose a location to apply
AE
Physical Design Engineer II (IC)
Arrow Electronics
Full-time · San Jose, CA · $87,400 – $165,000
A physical design engineer needed to execute synthesis, place-and-route, and timing analysis for ASIC chip partitions while collaborating with architects and RTL designers to resolve implementation challenges. This role suits engineers with deep expertise in EDA tools and advanced node technologies who can manage tight schedules and drive design convergence.
Listed on Arrow Electronics’s careers site · Apply there ↗
Senior ASIC Timing Engineer, DFT
NVIDIA
Full-time · Santa Clara, CA · $136,000 – $264,500
NVIDIA is seeking an engineer to drive timing analysis and closure for design-for-test logic across their GPU and processor chips, working across multiple hierarchical levels and collaborating with multiple teams to meet timing constraints. This role suits someone with strong static timing analysis expertise and several years of experience closing timing on advanced semiconductor nodes.
Listed on NVIDIA’s careers site · Apply there ↗
Design Technology Co-Optimization (DTCO) Engineer, Design flow and Methodology
Samsung Semiconductor
Full-time · Austin, TX · $180,200 – $270,400
Samsung is seeking a highly experienced engineer to develop design and analysis flows for their advanced semiconductor technology, optimizing the interplay between process technology and chip design methodology. This role suits someone with deep expertise in CAD tools, digital design flows, and a track record of solving complex engineering challenges in high-performance computing.
Listed on Samsung Semiconductor’s careers site · Apply there ↗
Senior Physical Design Methodology Engineer, Innovus Flows
NVIDIA
$168,000 – $310,500
NVIDIA is seeking a senior physical design engineer to develop and optimize chip design methodologies across their product line, with focus on power, performance, and area efficiency on advanced semiconductor nodes. This role combines deep expertise in EDA tools and physical design flows with emerging opportunities to apply machine learning to accelerate design cycles.
Listed on NVIDIA’s careers site · Apply there ↗
Senior Physical Design and Timing Engineer
NVIDIA
Westford, MA · $168,000 – $310,500
Senior ASIC Timing Engineer role at NVIDIA focused on optimizing timing and physical design for high-frequency, low-power networking chips from synthesis through final layout. Suited for experienced engineers with deep expertise in static timing analysis, ECO implementation, and chip-level design optimization who want to contribute to industry-leading semiconductor products.
Listed on NVIDIA’s careers site · Apply there ↗