$168,000 – $310,500
Listed on NVIDIA’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
NVIDIA is seeking a senior physical design engineer to develop and optimize chip design methodologies across their product line, with focus on power, performance, and area efficiency on advanced semiconductor nodes. This role combines deep expertise in EDA tools and physical design flows with emerging opportunities to apply machine learning to accelerate design cycles.
Our summary, not NVIDIA’s wording. The full posting is on their site.
Skills this role names
- C++
- Cadence OrCAD/Allegro
- Clock Tree Synthesis
- Network Routing
- NumPy
- Perl
- Physical Design
- Python
- PyTorch
- scikit-learn
- SciPy
- Static Timing Analysis
- Tcl
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What they ask for
Required
- Master's degree in Electrical Engineering, Computer Engineering, or equivalent experience
- Minimum 7 years of physical design experience
- Track record of PPA improvements on advanced technology nodes
- Understanding of place, CTS, route, and post-route optimization
- Expertise in static timing analysis, extraction, and timing closure
- Low power design experience with UPF
- Knowledge of power distribution networks and manufacturability
- Proficiency in TCL, Perl, Python, or C++
- Understanding of EM and IR analysis
- Synthesis and hierarchical design knowledge
Nice to have
- Emphasis on physical design methodology and flow development
- Experience with ML models, LLMs, and agentic AI for EDA/PD problems
- Data analysis and ML library proficiency
- In-depth knowledge of Cadence EDA tool suite