Listed on Samsung Semiconductor’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
Lead a team of STA engineers in semiconductor design, taking ownership of timing closure, synthesis, and physical design optimization for advanced chips. This role suits experienced ASIC design professionals who excel at both technical execution and mentoring, with deep expertise in constraints, low-power design, and high-speed timing closure.
Our summary, not Samsung Semiconductor’s wording. The full posting is on their site.
Skills this role names
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What they ask for
Required
- BSEE or MSEE in electrical engineering
- 12+ years of ASIC design experience
- Hands-on technical expertise in synthesis and STA
- Strong written and oral communication
- Deep sub-micron design knowledge
- Experience leading hard-IP and SoC timing closure
- Functional and test mode constraint development
- Low power management understanding
- Perl or Tcl scripting
- Ability to mentor and lead teams
Nice to have
- Good understanding of APR flows
- Experience with constraint management tools
- Knowledge of cross-talk noise analysis
- GCA and VCLP experience