AE
$87,400 – $165,000
Listed on Arrow Electronics’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
A physical design engineer needed to execute synthesis, place-and-route, and timing analysis for ASIC chip partitions while collaborating with architects and RTL designers to resolve implementation challenges. This role suits engineers with deep expertise in EDA tools and advanced node technologies who can manage tight schedules and drive design convergence.
Our summary, not Arrow Electronics’s wording. The full posting is on their site.
Skills this role names
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What they ask for
Required
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field
- 7+ years of hands-on physical design and implementation experience
- Proficiency with EDA tools such as Innovus, Tempus, and Quantus
- Experience with synthesis, PnR, timing convergence, and physical verification
Nice to have
- 7+ years in physical design roles
- Ability to meet tight schedules and implement low-power design techniques
- System-on-Chip design and implementation experience
- Expertise in sub-7nm node technologies
- Strong TCL scripting skills for custom EDA flows