$143,800 – $230,000
Listed on Broadcom Inc.’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
This role leads static timing analysis and closure for ASIC designs, ensuring they meet performance targets across manufacturing and environmental variations. It suits engineers with deep expertise in timing constraints, sign-off tools, and automation who can drive complex multi-scenario analysis from RTL through physical design.
Our summary, not Broadcom Inc.’s wording. The full posting is on their site.
Skills this role names
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What they ask for
Required
- Bachelor's degree in Electrical Engineering or Computer Engineering
- Minimum 12 years of hands-on ASIC STA and timing constraints development
- Proficiency with Cadence or Synopsys sign-off tools
- Experience with on-chip variation derates and multi-mode multi-corner constraints
- Scripting proficiency in Tcl, Python, Perl, or Shell
- Strong problem-solving skills
- Effective team collaboration and communication