$168,000 – $310,500
Listed on NVIDIA’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
Senior ASIC Timing Engineer role at NVIDIA focused on optimizing timing and physical design for high-frequency, low-power networking chips from synthesis through final layout. Suited for experienced engineers with deep expertise in static timing analysis, ECO implementation, and chip-level design optimization who want to contribute to industry-leading semiconductor products.
Our summary, not NVIDIA’s wording. The full posting is on their site.
Skills this role names
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What they ask for
Required
- BS in Electrical or Computer Engineering with 8 years experience, or MS with 4+ years in synthesis and timing
- Hands-on experience in full-chip/sub-chip static timing analysis and timing constraints management
- Expertise in fixing timing paths through ECOs including crosstalk and noise analysis
- Expertise in physical design optimization including placement, routing, cell sizing, buffering, and logic restructuring
- Background in logic synthesis or logical equivalence checking
- Deep knowledge of industry standard EDA tools like PrimeTime or Tempus
- Proficiency in Python, Tcl, and Make for automation
Nice to have
- Domain-specific STA and timing convergence experience in CPUs, GPUs, network processors, or SOCs
- Understanding of DFT logic and DFT timing closure experience
- Knowledge of deep sub-micron technology and process variation effects
- Experience in methodology, flow development, or automation