$136,000 – $264,500
Listed on NVIDIA’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
NVIDIA is seeking an engineer to drive timing analysis and closure for design-for-test logic across their GPU and processor chips, working across multiple hierarchical levels and collaborating with multiple teams to meet timing constraints. This role suits someone with strong static timing analysis expertise and several years of experience closing timing on advanced semiconductor nodes.
Our summary, not NVIDIA’s wording. The full posting is on their site.
Skills this role names
Log in to see which of these are already on your profile.
What they ask for
Required
- BS in Electrical or Computer Engineering with 5+ years experience, or MS with 2+ years experience
- Hands-on experience with Static Timing Analysis and driving timing convergence at full-chip/sub-chip level on advanced technology nodes
- Expertise in analyzing and fixing timing paths through ECOs
- Expertise in developing timing constraints
- In-depth knowledge of industry-standard timing convergence tools
Nice to have
- Understanding of DFT logic and experience with DFT timing closure for scan, iJTAG, and other modes
- Background in domain-specific STA such as Serdes, Processor, IO, or SMVA
- Experience in methodology or workflow development