$220,920 – $311,890
Listed on Intel’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
A Physical Design Timing Engineer role focused on analyzing and optimizing timing, power, and performance for Intel's next-generation System-on-Chip products. This position suits experienced engineers with deep expertise in static timing analysis, SoC clocking, and cross-functional collaboration who want to shape the future of semiconductor design.
Our summary, not Intel’s wording. The full posting is on their site.
Skills this role names
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What they ask for
Required
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
- 12+ years of timing analysis or physical design experience (or 8+ years with Master's degree, or 6+ years with PhD)
- Proficiency in static timing analysis and timing constraint generation
- Experience with physical design tools, flows, and methodologies
- Knowledge of SoC clocking and timing budgeting
- Scripting capability in TCL
- Understanding of digital design fundamentals and power/performance optimization
Nice to have
- Signal and power integrity analysis experience
- Cross-functional collaboration demonstrated with architecture and design teams
- Problem-solving ability on complex, large-scale designs
- Experience with advanced process nodes
- Familiarity with industry-leading EDA tools