$129,400 – $207,000
Listed on Broadcom Inc.’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
Broadcom's ASIC Products Division seeks an experienced engineer to lead timing closure and analysis for high-performance chip designs, working across design and physical implementation teams. This role suits someone with deep expertise in static timing analysis and a track record managing complex timing challenges in advanced semiconductor technologies.
Our summary, not Broadcom Inc.’s wording. The full posting is on their site.
Skills this role names
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What they ask for
Required
- 5–10 years hands-on STA experience
- MSEE degree or equivalent
- Understanding of timing margins from synthesis to sign-off
- Proficiency in STA tools and timing closure standards
- Knowledge of noise, cross-talk, and OCV effects
- Familiarity with circuit modeling and SPICE models
- Strong Perl and TCL programming skills
- Experience with large, high-performance SoC designs in sub-micron technologies
Nice to have
- 10+ years relevant industry experience
- Experience with Multi-Scenario Timing Closure
- Familiarity with ECO techniques and implementation
- Experience creating and maintaining analysis scripts and methodologies