48 open listings · Page 2 of 2
Roles posted by organizations here, alongside roles we found on employers’ own careers sites. Crawled roles say so on the card and send you to the employer to apply. Only show organizations on Career App
Design Technology Co-Optimization (DTCO) Engineer, Design flow and Methodology
Samsung Semiconductor
Full-time · Austin, TX · $180,200 – $270,400
Samsung is seeking a highly experienced engineer to develop design and analysis flows for their advanced semiconductor technology, optimizing the interplay between process technology and chip design methodology. This role suits someone with deep expertise in CAD tools, digital design flows, and a track record of solving complex engineering challenges in high-performance computing.
Listed on Samsung Semiconductor’s careers site · Apply there ↗
Director, Silicon Design Engineering
Intel
Full-time · $220,920 – $311,890
A Physical Design Timing Engineer role focused on analyzing and optimizing timing, power, and performance for Intel's next-generation System-on-Chip products. This position suits experienced engineers with deep expertise in static timing analysis, SoC clocking, and cross-functional collaboration who want to shape the future of semiconductor design.
Listed on Intel’s careers site · Apply there ↗
Staff Semiconductor Power Engineer (ICB4)
Broadcom Inc.
San Jose, CA · $121,900 – $195,000
A semiconductor design role focused on power management for advanced chips, requiring end-to-end ownership of power analysis and optimization across the design lifecycle. This suits engineers with deep expertise in power methodologies and EDA tools who can drive technical strategy across cross-functional teams.
Listed on Broadcom Inc.’s careers site · Apply there ↗
NVIDIA 2027 Internships: Hardware ASIC Design
NVIDIA
Internship · Santa Clara, CA · $20 – $71 / hour
NVIDIA is hiring interns for a 12-week full-time program focused on hardware ASIC design, where you'll contribute to real projects spanning chip architecture, physical design, and verification. The role suits students pursuing degrees in electrical or computer engineering who want hands-on experience with cutting-edge hardware development tools and methodologies.
Listed on NVIDIA’s careers site · Apply there ↗
DFT Implementation Engineer
Intel
Full-time · Austin, TX · $141,910 – $200,340
This role involves designing and implementing Design for Test capabilities into Intel's chip designs, working with RTL code and test methodologies to ensure manufacturability and quality. It suits experienced hardware engineers who want to influence product quality across multiple chip designs while collaborating with architecture, verification, and manufacturing teams.
Listed on Intel’s careers site · Apply there ↗
ASIC Implementation Engineer PD
Broadcom Inc.
San Jose, CA · $121,900 – $195,000
Broadcom seeks a physical design engineer to lead chip floorplanning and top-level integration for AI and PCIe switch products, from RTL through tape-out. This role suits experienced engineers with deep expertise in hierarchical floorplanning, clock trees, and cross-functional coordination across design and package teams.
Listed on Broadcom Inc.’s careers site · Apply there ↗
Senior DFT - Silicon Validation Engineer
NVIDIA
Santa Clara, CA · $168,000 – $310,500
NVIDIA seeks a seasoned design-for-test engineer to architect and execute silicon validation strategies for their most advanced semiconductor chips, leading the transition from design through production ramp. This role combines technical depth in DFT methodology with cross-functional leadership, suited for someone with years of hands-on chip validation experience who can drive yield and define next-generation test approaches.
Listed on NVIDIA’s careers site · Apply there ↗
R&D Engineer IC Design 4
Broadcom Inc.
2 locations · $121,900 – $195,000
This IC design role focuses on front-end logic design and verification of semiconductor cores, from architecture through physical implementation. It suits experienced engineers comfortable with the full ASIC flow who can manage complex timing and verification challenges independently and across distributed teams.
Listed on Broadcom Inc.’s careers site · Apply there ↗
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CAD Engineer
NVIDIA
Santa Clara, CA · $116,000 – $189,750
NVIDIA seeks a CAD engineer to support foundry techfiles, debug design issues, and develop automation scripts for circuit designers using industry-standard EDA tools. This role suits someone with strong programming skills who enjoys both technical problem-solving and working directly with designers across the chip design process.
Listed on NVIDIA’s careers site · Apply there ↗
ASIC Verification Engineer
Broadcom Inc.
2 locations · $101,000 – $162,000
This role develops verification environments and testbenches for high-speed communication ASICs, particularly Ethernet PHYs used in data center and networking products. It suits engineers with 3–5 years of HDL and verification experience who want to deepen their expertise in protocol validation and chip-level testing.
Listed on Broadcom Inc.’s careers site · Apply there ↗
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Senior PCB Library Engineer
NVIDIA
Full-time · Santa Clara, CA · $168,000 – $322,000
This role owns the creation and maintenance of PCB component libraries and design assets for NVIDIA's advanced computing platforms, requiring deep expertise in footprint development, manufacturing processes, and design standards. It suits experienced PCB engineers or component specialists who can bridge layout, manufacturing, and reliability concerns while driving quality and automation across a complex design ecosystem.
Listed on NVIDIA’s careers site · Apply there ↗
Senior Custom ASIC Engineering Lead
Broadcom Inc.
3 locations · $143,800 – $230,000
This is a senior engineering leadership role managing customer ASIC design programs across the full lifecycle, from initial requirements through production, with responsibility for guiding teams on advanced design practices and mitigating technical risks. It suits experienced chip design engineers comfortable with deep technical work, cross-functional collaboration, and advising both internal teams and external customers on complex semiconductor projects.
Listed on Broadcom Inc.’s careers site · Apply there ↗
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Formal Verification Engineer - New College Grad 2026
NVIDIA
Full-time · 2 locations · $100,000 – $166,750
NVIDIA seeks recent graduates to apply formal verification techniques to hardware design, proving the correctness of processors and accelerators through mathematical reasoning and specialized tools. This role suits analytically strong graduates excited about working with experienced engineers to catch bugs before silicon fabrication.
Listed on NVIDIA’s careers site · Apply there ↗
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Design Verification Engineer
Broadcom Inc.
5 locations · $143,800 – $230,000
Broadcom's ASIC division seeks a verification engineer to design and validate complex digital and mixed-signal IP blocks, from initial planning through coverage closure and debug. This role suits someone with deep SystemVerilog and UVM expertise who can architect reusable verification environments and work across block, system, and ASIC levels.
Listed on Broadcom Inc.’s careers site · Apply there ↗
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Custom SOC IP Verification Engineer
NVIDIA
Full-time · 2 locations · $168,000 – $310,500
NVIDIA is hiring a senior engineer to verify complex custom chip and interconnect designs, ensuring they work correctly and perform well across multiple integration levels. This role suits someone with deep ASIC verification experience who understands how on-chip fabrics connect different system components and can collaborate across architecture, design, and validation teams.
Listed on NVIDIA’s careers site · Apply there ↗
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Senior ASIC Design Engineer - DFT
NVIDIA
Santa Clara, CA · $168,000 – $310,500
NVIDIA is hiring a senior engineer to architect and implement design-for-test solutions for their next-generation AI chips, working across the full silicon lifecycle from design through post-silicon validation. This role suits someone with deep DFT expertise and SoC design experience who enjoys mentoring others and collaborating across hardware and software teams.
Listed on NVIDIA’s careers site · Apply there ↗
DFT ATPG Engineer
NVIDIA
This role leads automated test pattern generation and design-for-test implementations on NVIDIA's most advanced semiconductor chips, requiring deep expertise in ATPG tools and flows. It suits experienced hardware engineers who want to own complex testing solutions end-to-end across design, verification, and silicon validation.
Listed on NVIDIA’s careers site · Apply there ↗
Senior DFT Methodology - Data Analytics and Applied AI Engineer
NVIDIA
Santa Clara, CA · $152,000 – $230,000
NVIDIA seeks a senior engineer to develop data analytics and machine learning solutions for design-for-test methodology on advanced semiconductor chips, working with pre- and post-silicon data to solve complex validation challenges. This role suits engineers with strong backgrounds in data pipelines, statistical analysis, and applied AI who want to impact chip architecture at a leading semiconductor company.
Listed on NVIDIA’s careers site · Apply there ↗
Senior Physical Design Methodology Engineer, Innovus Flows
NVIDIA
$168,000 – $310,500
NVIDIA is seeking a senior physical design engineer to develop and optimize chip design methodologies across their product line, with focus on power, performance, and area efficiency on advanced semiconductor nodes. This role combines deep expertise in EDA tools and physical design flows with emerging opportunities to apply machine learning to accelerate design cycles.
Listed on NVIDIA’s careers site · Apply there ↗
Senior ASIC Physical Design Engineer, Netlisting
NVIDIA
$136,000 – $264,500
This Senior ASIC Physical Design Engineer role focuses on netlist-related work during chip design, handling logic equivalence checking, timing analysis, and synthesis for GPUs and SoCs at NVIDIA. It suits experienced hardware engineers with deep expertise in formal verification, EDA tools, and timing closure who want to work on cutting-edge AI computing hardware.
Listed on NVIDIA’s careers site · Apply there ↗
Senior Physical Design and Timing Engineer
NVIDIA
2 locations · $168,000 – $310,500
Senior ASIC Timing Engineer role at NVIDIA focused on optimizing timing and physical design for high-frequency, low-power networking chips from synthesis through final layout. Suited for experienced engineers with deep expertise in static timing analysis, ECO implementation, and chip-level design optimization who want to contribute to industry-leading semiconductor products.
Listed on NVIDIA’s careers site · Apply there ↗
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Senior Physical Design Engineer
NVIDIA
Full-time · 3 locations · $136,000 – $264,500
NVIDIA is seeking experienced physical design engineers to lead the design and implementation of networking silicon chips, from RTL through production tape-out. This role suits engineers with deep expertise in advanced node physical design who can drive complex chip development workflows and mentor a team through the full design cycle.
Listed on NVIDIA’s careers site · Apply there ↗
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Physical Design Engineer, Synthesis and Implementation
NVIDIA
Full-time · Westford, MA · $116,000 – $218,500
NVIDIA seeks a Physical Design Engineer to optimize chip synthesis and physical implementation for high-speed networking processors, working across RTL-to-gate flows and collaborating with multiple engineering teams to meet performance and area targets on advanced process nodes.
Listed on NVIDIA’s careers site · Apply there ↗