57 open listings · Page 2 of 3
Roles posted by organizations here, alongside roles we found on employers’ own careers sites. Crawled roles say so on the card and send you to the employer to apply. Only show organizations on Career App
Analog/Mixed Signal Verilog Modeling Design Engineer
Broadcom Inc.
This role develops behavioral models of analog circuit blocks in SystemVerilog for chip verification, bridging the analog design and digital verification teams. It suits engineers with strong analog circuit knowledge who can code detailed mixed-signal simulations and validate them against schematics.
Listed on Broadcom Inc.’s careers site · Apply there ↗
AE
Physical Design Engineer II (eInfochips Inc)
Arrow Electronics
Full-time · San Jose, CA
This role executes the physical design and place-and-route phases of ASIC chip development, collaborating with RTL and architecture teams to meet timing and power targets through the full implementation flow. It suits engineers with 7+ years of hands-on EDA tool experience who want to work on advanced-node chip design at scale.
Listed on Arrow Electronics’s careers site · Apply there ↗
Senior Staff Engineer, Physical Implementation CAD Lead
Samsung Semiconductor
Full-time · $180,200 – $297,200
Samsung is seeking a senior engineer to lead physical design CAD methodology development for GPU and SoC chips at advanced technology nodes. This role suits an expert in place-and-route tools and sub-5nm design challenges who can drive automation, mentor teams, and collaborate across EDA vendors and internal design groups.
Listed on Samsung Semiconductor’s careers site · Apply there ↗
Senior DFT Methodology - Data Analytics and Applied AI Engineer
NVIDIA
Santa Clara, CA · $152,000 – $230,000
NVIDIA seeks a senior engineer to develop data analytics and machine learning solutions for design-for-test methodology on advanced semiconductor chips, working with pre- and post-silicon data to solve complex validation challenges. This role suits engineers with strong backgrounds in data pipelines, statistical analysis, and applied AI who want to impact chip architecture at a leading semiconductor company.
Listed on NVIDIA’s careers site · Apply there ↗
Director, Silicon Design Engineering
Intel
Full-time · $220,920 – $311,890
A Physical Design Timing Engineer role focused on analyzing and optimizing timing, power, and performance for Intel's next-generation System-on-Chip products. This position suits experienced engineers with deep expertise in static timing analysis, SoC clocking, and cross-functional collaboration who want to shape the future of semiconductor design.
Listed on Intel’s careers site · Apply there ↗
Staff Semiconductor Power Engineer (ICB4)
Broadcom Inc.
San Jose, CA · $121,900 – $195,000
A semiconductor design role focused on power management for advanced chips, requiring end-to-end ownership of power analysis and optimization across the design lifecycle. This suits engineers with deep expertise in power methodologies and EDA tools who can drive technical strategy across cross-functional teams.
Listed on Broadcom Inc.’s careers site · Apply there ↗
AE
Physical Design Engineer II (IC)
Arrow Electronics
Full-time · San Jose, CA · $87,400 – $165,000
A physical design engineer needed to execute synthesis, place-and-route, and timing analysis for ASIC chip partitions while collaborating with architects and RTL designers to resolve implementation challenges. This role suits engineers with deep expertise in EDA tools and advanced node technologies who can manage tight schedules and drive design convergence.
Listed on Arrow Electronics’s careers site · Apply there ↗
Sr. Staff Physical Design PPA Engineer
Samsung Semiconductor
Full-time · Austin, TX · $180,200 – $270,400
Samsung seeks a senior physical design engineer to lead power, performance, and area optimization initiatives across their GPU and custom semiconductor IP. This role suits experienced design implementation professionals who excel at problem-solving, understand chip design flows deeply, and can drive methodology improvements across synthesis, place-and-route, and signoff.
Listed on Samsung Semiconductor’s careers site · Apply there ↗
Senior Physical Design Methodology Engineer, Innovus Flows
NVIDIA
$168,000 – $310,500
NVIDIA is seeking a senior physical design engineer to develop and optimize chip design methodologies across their product line, with focus on power, performance, and area efficiency on advanced semiconductor nodes. This role combines deep expertise in EDA tools and physical design flows with emerging opportunities to apply machine learning to accelerate design cycles.
Listed on NVIDIA’s careers site · Apply there ↗
DFT Implementation Engineer
Intel
Full-time · Austin, TX · $141,910 – $200,340
This role involves designing and implementing Design for Test capabilities into Intel's chip designs, working with RTL code and test methodologies to ensure manufacturability and quality. It suits experienced hardware engineers who want to influence product quality across multiple chip designs while collaborating with architecture, verification, and manufacturing teams.
Listed on Intel’s careers site · Apply there ↗
Signal Integrity Engineer
Broadcom Inc.
2 locations · $143,800 – $230,000
Broadcom's ASIC Products Division seeks a signal integrity engineer to design and validate advanced interconnect technologies for AI, cloud, and networking applications. This role blends customer-facing technical work with internal R&D, requiring expertise in high-speed signal and power analysis for cutting-edge 2.5D and 3D chip packaging.
Listed on Broadcom Inc.’s careers site · Apply there ↗
Choose a location to apply
AE
Design For Test Engineer III (IC)
Arrow Electronics
Full-time · San Jose, CA · $95,900 – $170,500
This role involves designing and implementing Design For Test solutions for advanced networking chips at 3nm and 5nm nodes, working with industry-standard tools like Tessent and Tetramax to develop test patterns, verify memory and JTAG functionality, and automate DFT flows through scripting. It suits experienced DFT engineers who have worked on complex SoCs and want to apply their expertise in semiconductor test methodology at a large global company.
Listed on Arrow Electronics’s careers site · Apply there ↗
Senior Staff Physical Design Feasibility Engineer
Samsung Semiconductor
Full-time · Austin, TX · $180,200 – $270,400
Samsung is seeking a senior physical design engineer to lead the optimization and feasibility of complex GPU and ASIC designs from planning through tape-out, ensuring performance, power, and area targets are met. This role suits experienced chip designers who want to work on high-performance mobile and automotive processors at a world-class semiconductor company.
Listed on Samsung Semiconductor’s careers site · Apply there ↗
Hardware Test Engineer - Silicon Validation
NVIDIA
Santa Clara, CA · $132,000 – $207,000
This role leads the design and operation of NVIDIA's global hardware testing infrastructure for silicon validation, overseeing farms of GPU and processor systems and driving automation across the validation lifecycle. It suits experienced hardware engineers who can coordinate across teams, debug complex systems, and build scalable test infrastructure.
Listed on NVIDIA’s careers site · Apply there ↗
Senior Physical Design Engineer (CPU)
Intel
Full-time · Hillsboro, OR · $141,910 – $269,100
This role involves owning the physical design and implementation of CPU core blocks, executing the full RTL-to-GDS flow including synthesis, place-and-route, and timing closure. It suits experienced hardware engineers with deep expertise in digital design tools and a track record of shipping complex silicon at advanced process nodes.
Listed on Intel’s careers site · Apply there ↗
ASIC Implementation Engineer STA
Broadcom Inc.
Full-time · San Jose, CA · $143,800 – $230,000
This role leads static timing analysis and closure for ASIC designs, ensuring they meet performance targets across manufacturing and environmental variations. It suits engineers with deep expertise in timing constraints, sign-off tools, and automation who can drive complex multi-scenario analysis from RTL through physical design.
Listed on Broadcom Inc.’s careers site · Apply there ↗
Senior Staff Engineer, Physical Design (Floorplanning)
Samsung Semiconductor
Full-time · Austin, TX · $180,200 – $270,400
Samsung is seeking a Senior Staff GPU Physical Design Engineer to lead floorplanning and power-grid implementation for next-generation high-performance GPU and system-level designs. This role suits experienced physical design engineers who can drive methodology innovation, mentor others, and deliver silicon across advanced technology nodes.
Listed on Samsung Semiconductor’s careers site · Apply there ↗
Senior Physical Design and Timing Engineer
NVIDIA
Westford, MA · $168,000 – $310,500
Senior ASIC Timing Engineer role at NVIDIA focused on optimizing timing and physical design for high-frequency, low-power networking chips from synthesis through final layout. Suited for experienced engineers with deep expertise in static timing analysis, ECO implementation, and chip-level design optimization who want to contribute to industry-leading semiconductor products.
Listed on NVIDIA’s careers site · Apply there ↗
ASIC Implementation Engineer PD
Broadcom Inc.
San Jose, CA · $121,900 – $195,000
Broadcom seeks a physical design engineer to lead chip floorplanning and top-level integration for AI and PCIe switch products, from RTL through tape-out. This role suits experienced engineers with deep expertise in hierarchical floorplanning, clock trees, and cross-functional coordination across design and package teams.
Listed on Broadcom Inc.’s careers site · Apply there ↗
DFT Application Engineer
Intel
Full-time · $122,440 – $232,190
This role supports Intel Foundry Services customers with design-for-test implementation on advanced semiconductor processes, combining technical customer support with methodology development and training. It suits experienced engineers with ASIC DFT expertise who want to work on high-reliability aerospace and defense applications while engaging directly with customers.
Listed on Intel’s careers site · Apply there ↗
Design Technology Co-Optimization (DTCO) Engineer, Design flow and Methodology
Samsung Semiconductor
Full-time · Austin, TX · $180,200 – $270,400
Samsung is seeking a highly experienced engineer to develop design and analysis flows for their advanced semiconductor technology, optimizing the interplay between process technology and chip design methodology. This role suits someone with deep expertise in CAD tools, digital design flows, and a track record of solving complex engineering challenges in high-performance computing.
Listed on Samsung Semiconductor’s careers site · Apply there ↗
Senior Physical Design Engineer
NVIDIA
Full-time · 2 locations · $136,000 – $264,500
NVIDIA is seeking experienced physical design engineers to lead the design and implementation of networking silicon chips, from RTL through production tape-out. This role suits engineers with deep expertise in advanced node physical design who can drive complex chip development workflows and mentor a team through the full design cycle.
Listed on NVIDIA’s careers site · Apply there ↗
Choose a location to apply
STA Engineer
Broadcom Inc.
Fort Collins, CO · $129,400 – $207,000
Broadcom's ASIC Products Division seeks an experienced engineer to lead timing closure and analysis for high-performance chip designs, working across design and physical implementation teams. This role suits someone with deep expertise in static timing analysis and a track record managing complex timing challenges in advanced semiconductor technologies.
Listed on Broadcom Inc.’s careers site · Apply there ↗
Senior Applications and Solutions Engineer - Foundry Services
Intel
Full-time · $122,440 – $232,190
Intel Foundry Services needs a senior design engineer to guide customers through complex chip designs using advanced multi-voltage techniques and EDA tools, while also improving design documentation and reference flows for the foundry platform. This role suits experienced ASIC designers comfortable with low-power and power-domain verification methodologies who want to shift into technical customer support and design methodology leadership.
Listed on Intel’s careers site · Apply there ↗
Physical Design Engineer, Synthesis and Implementation
NVIDIA
Full-time · Westford, MA · $116,000 – $218,500
NVIDIA seeks a Physical Design Engineer to optimize chip synthesis and physical implementation for high-speed networking processors, working across RTL-to-gate flows and collaborating with multiple engineering teams to meet performance and area targets on advanced process nodes.
Listed on NVIDIA’s careers site · Apply there ↗