$121,900 – $195,000
Listed on Broadcom Inc.’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
Broadcom seeks a physical design engineer to lead chip floorplanning and top-level integration for AI and PCIe switch products, from RTL through tape-out. This role suits experienced engineers with deep expertise in hierarchical floorplanning, clock trees, and cross-functional coordination across design and package teams.
Our summary, not Broadcom Inc.’s wording. The full posting is on their site.
Skills this role names
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What they ask for
Required
- Floorplanning expertise in die size estimation, partitioning, clocking, and pin planning
- Experience resolving chip-level DRC/LVS/EMIR issues on advanced nodes
- On-site work required at San Jose location
Nice to have
- Bachelor's degree in Electrical Engineering with 8+ years of top-level floorplanning experience, or Master's degree with 6+ years
- Experience with Switch Fabric, Arbiter, High Speed DDR, SerDes, HBM, D2D I/O, and chiplet technologies
- Track record with bump planning, RDL implementation, and multi-voltage domain designs
- Hierarchical floorplanning and structured clock experience
- Collaboration experience with design, package, and methodology teams
- Scripting language proficiency