$168,000 – $310,500
Listed on NVIDIA’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
NVIDIA seeks a seasoned design-for-test engineer to architect and execute silicon validation strategies for their most advanced semiconductor chips, leading the transition from design through production ramp. This role combines technical depth in DFT methodology with cross-functional leadership, suited for someone with years of hands-on chip validation experience who can drive yield and define next-generation test approaches.
Our summary, not NVIDIA’s wording. The full posting is on their site.
What they ask for
Required
- BSEE with 8+ years experience, MSEE with 5+ years, or PhD with 3+ years in DFT or related domains
- Expertise in silicon debug and DFT productization
- Demonstrated leadership in yield ramp and waste reduction across multiple products
- Hands-on pre-silicon validation experience for DFT features
- Strong written and oral communication skills
Nice to have
- Proven track record implementing advanced DFT methodologies in groundbreaking semiconductor technologies
- Strong knowledge of high-speed protocols and semiconductor process technology
- Knowledge of industry-standard DFT tools and software
- Strong problem-solving skills and proactive approach to technical challenges
- Programming and scripting in Perl, Python, or Tcl