$122,440 – $232,190
Listed on Intel’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
This role involves designing and optimizing physical implementations of CPU core blocks through synthesis, placement, routing, and timing closure on advanced semiconductor nodes. It suits engineers with 3-5+ years of IC design experience who want to deepen their expertise in digital design while collaborating across teams on world-class processor platforms.
Our summary, not Intel’s wording. The full posting is on their site.
Skills this role names
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What they ask for
Required
- Bachelor's degree in Computer or Electrical Engineering or related field with 5+ years relevant experience, or Master's degree with 3+ years relevant experience
- Experience with IC design tools (Synopsys/Cadence) including logic synthesis, place and route, static timing analysis, and design closure
- PV convergence including static timing and power analysis
- Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, noise, and electromigration checks
- Scripting in TCL plus at least one other interpreted language (Perl, Python, or Ruby)
- Experience with synthesis of a digital logic block integrated into a large SoC or IP
Nice to have
- Industry experience or exposure with CPU microarchitecture
- Knowledge of physical design best practices for floor-planning, routing, and clock distribution
- Expertise in static timing analysis, noise analysis, and reliability verification techniques
- Experience with RTL to GDS methodologies and formal equivalence
- Proficiency with Synopsys tool suite (Fusion Compiler, ICC2, PrimeTime) or Cadence (Genus/Innovus)