$129,400 – $207,000
Listed on Broadcom Inc.’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
This role involves developing comprehensive verification testbenches for high-performance Ethernet ASICs used in cloud and AI/ML applications, using constrained random methodologies to ensure design correctness. You'll work with senior engineers across design and architecture teams to verify complex silicon that pushes the boundaries of throughput and power efficiency.
Our summary, not Broadcom Inc.’s wording. The full posting is on their site.
Skills this role names
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What they ask for
Required
- 12+ years experience in design verification (or 10+ with Masters, or 3+ with PhD)
- Constrained random verification methodologies
- Coverage-driven closure experience
- SystemVerilog testbench development
- UVM framework experience
Nice to have
- Python or Perl scripting
- Advanced SystemVerilog features (assertions, classes)
- Deep OOP understanding