MP
$320,000 – $485,000
Listed on Menlo Ventures Portfolio’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
Anthropic is building a custom silicon team to support their massive AI training and inference workloads, and seeks an experienced engineer to own end-to-end technical decisions across domains like design, verification, or physical implementation. This role suits someone who has shipped silicon before, can operate independently on a small founding team, and is comfortable making architecture calls and working with external partners.
Our summary, not Menlo Ventures Portfolio’s wording. The full posting is on their site.
Skills this role names
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What they ask for
Required
- Deep hands-on expertise in at least one silicon domain: front-end design, pre-silicon verification, physical design, design for test, analog and mixed-signal, technology and foundry, CAD infrastructure, or packaging and signal/power integrity
- Direct personal contribution to silicon that taped out and shipped with demonstrable ownership
- Fluency in adjacent silicon domains sufficient to reason about chip-level tradeoffs
- Experience partnering with external vendors including ASIC houses, IP vendors, foundries, and test partners
- Track record of owning directional technical decisions and their consequences
- Practical experience using AI coding tools and clear assessment of their effectiveness
- Strong written and verbal communication with experience driving cross-team alignment
- Ability to operate with high autonomy on a dynamic program with minimal scaffolding
- Bachelor's degree or equivalent combination of education and professional experience
Nice to have
- Experience on machine learning accelerators or high-performance compute designs
- Experience founding or joining an early-stage silicon team and building flows or tooling from scratch
- Familiarity with both partner-executed and fully in-house silicon programs
- Understanding of chip-package-system interface tradeoffs
- Hardware-software co-design experience working directly with compiler, kernel, or runtime teams
- Experience building or extending AI-assisted design, verification, or physical design flows
- Depth in memory subsystems, on-die interconnect, numerics, or low-power design