$143,800 – $230,000
Listed on Broadcom Inc.’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
This role focuses on integrating and verifying IP blocks within SoCs using RTL design and simulation, requiring expertise in CDC analysis, synthesis, and gate-level debugging. It suits engineers with 12+ years of experience in design verification and implementation who can work independently on complex timing and cross-domain challenges.
Our summary, not Broadcom Inc.’s wording. The full posting is on their site.
What they ask for
Required
- 12+ years of related experience
- Bachelor's degree
- Extensive knowledge of implementation, synthesis, and timing issues
- Strong understanding of UVM and SystemVerilog
- Deep familiarity with zero-delay and SDF simulations and debugging
- Proven gate-level simulation experience
- Familiarity with CDC analysis for RTL and gate-level designs
- Ability to work independently with minimal supervision
- Strong debugging skills
Nice to have
- Experience with NCSim and VCS simulation tools
- Experience working in global teams
- Strong ability to learn and adapt to new tools and methodologies