AE
$95,900 – $170,500
Listed on Arrow Electronics’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
This role involves designing and implementing Design For Test solutions for advanced networking chips at 3nm and 5nm nodes, working with industry-standard tools like Tessent and Tetramax to develop test patterns, verify memory and JTAG functionality, and automate DFT flows through scripting. It suits experienced DFT engineers who have worked on complex SoCs and want to apply their expertise in semiconductor test methodology at a large global company.
Our summary, not Arrow Electronics’s wording. The full posting is on their site.
What they ask for
Required
- 5–7 years of DFT experience
- Scan insertion and ATPG pattern generation
- Pattern simulation with and without timing
- MBIST insertion and verification
- IEEE 1149.1 JTAG insertion and verification
- Scripting in Perl, Shell, or TCL
- Experience on multi-million gate count SoCs
- Mentor Tessent experience
- B.Tech or M.Tech in Microelectronics or Electronics
Nice to have
- Networking, Consumer, or IP block (PLL, Serdes) experience
- Low power DFT experience