$122,440 – $172,860
Listed on Intel’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
Intel is hiring an Analog Layout Design Engineer to create and optimize layouts for analog signal circuits in semiconductor designs. This role suits engineers with experience in analog device layout, Cadence tools, and CMOS technologies who want to work on cutting-edge chip design with cross-functional teams.
Our summary, not Intel’s wording. The full posting is on their site.
What they ask for
Required
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 3+ years of experience, or Master's degree with 2+ years
- Analog device and metal layout fundamentals including analog/mixed-signal understanding
- Cadence Virtuoso Layout Suite and Calibre/ICV DRC proficiency
- CMOS technologies and high-voltage rules knowledge
- Floor planning and hierarchical layout planning for analog and mixed-signal blocks
- Layout performance verification and debug capabilities
Nice to have
- Strong understanding of analog layout effects such as mismatch, parasitics, IR drop, and electromigration
- Application of common-centroid, interdigitation, and symmetry-based layout techniques
- Process variation and gradient effect evaluation and mitigation
- Parasitic-aware design using extraction and simulation tools
- Debugging layout issues by correlating LVS, DRC, extraction, and silicon behavior
- Noise isolation, shielding, and signal integrity optimization in mixed-signal environments