$168,000 – $310,500
Listed on NVIDIA’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
NVIDIA seeks an experienced engineer to design and implement validation strategies, telemetry infrastructure, and AI-assisted tools for low-power silicon features across next-generation AI accelerators. The role bridges silicon architecture, firmware, and platform validation to improve power efficiency and production readiness at scale.
Our summary, not NVIDIA’s wording. The full posting is on their site.
Skills this role names
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What they ask for
Required
- BS or MS in EE, CE, CS, or Systems Engineering, or equivalent experience
- 10+ years in silicon characterization, low-power validation, system integration, or post-silicon productization
- Deep understanding of silicon power behavior, Windows/Linux low-power states, firmware interactions, and system-level validation methodologies
- Experience building scalable automation or telemetry analytics for silicon validation
- Strong EE fundamentals including digital design, computer architecture, power analysis, and programming
- Hands-on silicon bring-up, lab validation, and debug experience
Nice to have
- Experience applying AI/ML or LLM to silicon validation, telemetry analytics, or debug automation
- Background in platform power management technologies like S0ix, ASPM, RTD3, or Memory Self Refresh
- Large-scale telemetry pipeline or intelligent observability infrastructure development
- Strong Python and data analytics expertise
- Cross-functional experience spanning architecture, firmware, silicon validation, and manufacturing