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NVIDIA

Principal Chip Lead, Silicon Co-Design Group

NVIDIA

Santa Clara, CA · full time · Principal

$232,000 – $368,000

Listed on NVIDIA’s own careers site. You apply with them directly — we never stand between you and the employer.

What this role is

A technical leadership role guiding one of NVIDIA's most critical silicon programs through multi-functional challenges from architecture to production. This suits someone with 15+ years of semiconductor experience who thrives as a bridge between engineering disciplines, solving hard problems without direct authority.

Our summary, not NVIDIA’s wording. The full posting is on their site.

Skills this role names

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What they ask for

Required

  • 15+ years semiconductor industry experience
  • BS or MS in Electrical or Computer Engineering or equivalent
  • Track record in post-silicon bring-up, validation, or system integration leadership at major semiconductor company
  • Multiple shipped silicon products
  • End-to-end SoC and ASIC architecture understanding
  • Recognized expertise in at least one subsystem: HBM, SerDes, power/thermal, or packaging
  • Specific examples of silicon-level impact: faster bring-up, fewer escapes, yield recovery, or methodology contributions
  • Experience guiding technical decisions across functional boundaries without direct reporting authority
  • Ability to translate complex silicon issues into clear options for executive audiences

Nice to have

  • Prior experience as Chip Lead, Project Tech Lead, Principal or Distinguished Engineer on flagship GPU, AI accelerator, CPU, or networking ASIC
  • Patents, conference papers, invited talks, or recognized contributions to silicon validation or co-design integration
  • History of building and sharing reusable technical methodology across programs: playbooks, debug frameworks, or adopted standards
  • Hands-on debug experience with HBM, high-speed I/O, power/thermal, or packaging
  • Comfort with globally distributed teams
  • Experience using AI tools to improve team velocity
  • External representation and early risk communication experience

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