Listed on Samsung Semiconductor’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
This role leads physical verification and electrical analysis for advanced semiconductor chip designs at Samsung's major R&D center in India, overseeing signoff activities across multiple verification domains. It suits experienced chip designers who have worked on cutting-edge process nodes and can mentor junior engineers while driving process improvements.
Our summary, not Samsung Semiconductor’s wording. The full posting is on their site.
What they ask for
Required
- 11 to 18 years of experience in semiconductor physical design and verification
- Experience with low-technology nodes (8nm, 5nm, 3nm, or 2nm)
- Expertise in physical verification methodologies and sign-off processes
- Ability to develop and manage automated verification flows and scripts
- Bachelor's or Master's degree in engineering
Nice to have
- Technical leadership experience mentoring junior engineers
- Knowledge of design-for-test (DfT) collaboration
- Familiarity with package and technology integration