$196,000 – $368,000
Listed on NVIDIA’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
This role involves developing design-for-test power methodology for NVIDIA's datacenter GPUs, working on low-power solutions, thermal management, and post-silicon analysis. It suits senior chip design engineers with deep DFT and power expertise who enjoy solving complex semiconductor manufacturing challenges and mentoring others.
Our summary, not NVIDIA’s wording. The full posting is on their site.
Skills this role names
Log in to see which of these are already on your profile.
What they ask for
Required
- 12+ years DFT design and power experience (or MSEE with 10+ years, or PhD with 6+ years)
- Understanding of DFT fundamentals and VLSI power, timing, and voltage noise
- Statistical tools expertise for data analysis
- Multi-functional knowledge including RTL, clocks, STA, place-and-route, and power
- Silicon debug and bring-up experience on ATE or SLT platforms
- Ability to apply programming concepts to AI coding harnesses
- Strong written and oral communication skills
Nice to have
- Power Analysis, Thermal Analysis, and IR Drop tools experience
- AI application for EDA problem-solving
- DFT Power Methodology management experience
- Post-silicon debug experience for thermal and IR Drop
- Deep technology understanding and passion