Listed on Samsung Semiconductor’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
Samsung Semiconductor India seeks a Design for Test engineer with deep expertise in semiconductor verification and BIST architectures to lead DFT activities from concept through silicon validation. This senior role suits someone with 12-20 years' experience working across scan design, memory testing, and complex verification methodologies on cutting-edge semiconductor products.
Our summary, not Samsung Semiconductor’s wording. The full posting is on their site.
What they ask for
Required
- 12-20 years DFT experience with end-to-end involvement from concept to silicon bring-up
- Scan and MBIST architecture design fundamentals
- Implementation and verification across RTL, gate-level and SDF simulation
- SDC constraint development
- Post-silicon debug and issue resolution
- B.Tech/B.E/M.Tech/M.E degree
Nice to have
- Custom BIST design experience
- Cross-functional team collaboration
- Attention to detail and quality review practices