$232,000 – $368,000
Listed on NVIDIA’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
Lead the end-to-end post-silicon execution for complex GPU and SoC products, from first power-on through production ramp, driving technical and program outcomes across distributed teams. This role suits experienced engineering leaders with deep expertise in silicon bring-up, debug, and validation who can operate effectively across hardware and software domains under aggressive schedules.
Our summary, not NVIDIA’s wording. The full posting is on their site.
Skills this role names
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What they ask for
Required
- BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience
- 12+ years overall experience
- 5+ years management experience
- Significant leadership in post-silicon bring-up, validation, debug, or productization for complex SoCs, GPUs, ASICs, or systems
- Led teams through first-silicon bring-up, issue triage, debug closure, and production transition
- Deep technical understanding of digital design, computer or system architecture, power, timing, clocking, reset, noise, and fault analysis
- Strong experience with post-silicon debug and validation flows, lab execution, test planning, and data-driven issue management
- Ability to work across pre-silicon and post-silicon teams and influence senior partners across organizational boundaries
- Strong communication and interpersonal skills
Nice to have
- Experience leading bring-up for both SoC and GPU-class silicon or highly integrated platform programs
- Hands-on experience with first power-on, system bring-up, silicon characterization, binning, reliability qualification, or production ramp
- Experience building bring-up methodologies, debug infrastructure, or validation frameworks across multiple product generations
- Strong background in firmware, low-level software, or hardware-software co-debug for complex systems
- Experience driving pre-silicon execution including multi-functional planning through design, verification, and tapeout readiness