$151,000 – $251,800
Listed on Samsung Semiconductor’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
Samsung is seeking a senior microarchitecture engineer to lead the design of coherent interconnect and cache IP for high-performance computing systems. This role combines architectural innovation with RTL implementation, requiring deep expertise in cache protocols, on-chip networks, and ASIC design flows across a collaborative team building solutions for millions of devices worldwide.
Our summary, not Samsung Semiconductor’s wording. The full posting is on their site.
What they ask for
Required
- 10+ years experience with Bachelor's degree in Computer Science/Engineering, or 8+ years with Master's degree, or 6+ years with PhD
- RTL design ownership of coherent interconnect, memory controller, or LLC blocks
- Verilog expertise and deep understanding of ASIC design flow
- Knowledge of system caches and directory snoop filter protocols
- Familiarity with on-chip network topologies: mesh, ring, crossbar
- Team leadership and mentoring experience
- Knowledge of Arm AMBA5 CHI, AMBA4 ACE, or AXI coherent interconnect protocols
- Memory subsystem design experience including coherent cache design
Nice to have
- Verilog/VHDL and scripting expertise
- STA, DFT, ECO workflow knowledge
- Proficiency in AMBA, ACE, AXI, CHI protocols
- Coherent interconnect, memory controller, and cache design experience
- Memory subsystem and coherency protocol knowledge
- Scripting language experience: Perl or Python