$149,600 – $284,580
Listed on Intel’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
This role develops electrostatic discharge verification rule sets and methodologies for Intel's most advanced semiconductor process technologies, enabling design teams to deliver products faster. It suits engineers with strong physical design verification backgrounds who want to solve complex reliability challenges at the cutting edge of semiconductor manufacturing.
Our summary, not Intel’s wording. The full posting is on their site.
What they ask for
Required
- Master's degree or PhD in Electrical Engineering or Computer Engineering
- 3+ years of physical design verification experience in reliability, device physics, process technology, or design rules
- 2+ years of ESD PERC rule deck or reliability/DRC tools development and debugging
- 2+ years of scripting experience (Python, Tcl, Perl, or similar) for QA and automation
Nice to have
- Deep knowledge of ESD/LU PreSi models (HBM, CDM) and I/O design methodologies
- Strong analytical and problem-solving abilities with independent thinking
- Excellent attention to detail and organizational skills
- Cross-disciplinary approach to solution design
- Leadership skills and ability to influence internal and external stakeholders
- Clear communication of complex technical concepts
- Experience with cross-functional and cross-site team collaboration
- Proven ability to drive cross-functional or industry-wide initiatives