$143,800 – $230,000
Listed on Broadcom Inc.’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
Broadcom seeks a Physical Design Engineer to lead chip floorplanning and physical implementation from RTL through silicon tape-out, focusing on next-generation AI and PCIe Switch products. This role suits senior engineers with deep expertise in top-level floorplanning, clock trees, and cross-functional coordination across design, package, and methodology teams.
Our summary, not Broadcom Inc.’s wording. The full posting is on their site.
What they ask for
Required
- Bachelor's in Electrical Engineering with 12+ years in top-level floorplanning, or Master's in Electrical Engineering with 10+ years
- Experience with die size estimation, partitioning, clocking, and pin planning
- On-site work in San Jose, no remote option
Nice to have
- Experience with Switch Fabric, Arbiter, High Speed DDR, SerDes, HBM, D2D I/O, or chiplet technologies
- Chip-level DRC/LVS/EMIR resolution on advanced nodes
- Multi-voltage domain design
- Structured clocks and top-level pipeline planning
- Collaboration experience with design, package, and methodology teams