$128,880 – $245,160
Listed on Intel’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
This role supports Intel's foundry customers with advanced semiconductor layout verification and parasitic extraction challenges, focusing on aerospace and defense applications. It suits experienced engineers who can provide technical leadership, develop verification methodologies, and guide customers through complex physical design problems on cutting-edge process nodes.
Our summary, not Intel’s wording. The full posting is on their site.
Skills this role names
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What they ask for
Required
- US citizenship
- Ability to obtain US Government Security Clearance
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or STEM field
- 3+ years experience with advanced CMOS processes 22nm and below
- 3+ years combined experience with layout verification and parasitic extraction EDA tools
- 3+ years experience with Python, Perl, Tcl, or shell scripting
Nice to have
- Active US Government Security Clearance at Secret level or higher
- Post-graduate degree in Electrical Engineering, Computer Engineering, Computer Science, or STEM field
- Hands-on experience with LVS, DRC, ERC, or PERC
- Experience with StarRC, Quantus, or xACT parasitic extraction tools
- Experience with ICV, Calibre, or Pegasus layout editing tools
- Rule deck coding experience in ICV, Calibre, or Pegasus
- Experience providing technical direction to engineering teams
- Customer-facing technical support experience