$136,000 – $264,500
Listed on NVIDIA’s own careers site. You apply with them directly — we never stand between you and the employer.
What this role is
Design and optimize voltage noise and power delivery across chip, package, and board for next-generation silicon, working across multiple teams to translate product targets into shipped specifications and drive show-stopper issues to closure.
Our summary, not NVIDIA’s wording. The full posting is on their site.
Skills this role names
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What they ask for
Required
- BS/MS/PhD in EE, CE, or related field or equivalent experience
- 5+ years in silicon power integrity, voltage noise, or PDN
- Deep expertise in at least one of: di/dt analysis and mitigation, voltage droop, PDN design, transient noise, or decap budgeting
- Hands-on silicon bringup, characterization, and correlation experience
- Strong simulation-to-silicon correlation skills
- System-level thinking and ability to make decisions across competing requirements
- Multi-functional collaboration in matrix environments
- Spec documentation rigor and closure discipline
Nice to have
- Patents or publications in power integrity or related areas
- Experience with groundbreaking GPU, CPU, or AI accelerator silicon (Hopper/Blackwell class)
- ML/AI applied to noise modeling, transient prediction, or droop response
- Multi-rail, multi-domain PDN ownership at SoC level across die, package, and board
- Track record of codifying methodology into reusable workflows or tooling