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Intel

Lead Analog SerDes Architect/Design Engineer

Intel

Santa Clara, CA · full time · Senior

$220,920 – $311,890

Listed on Intel’s own careers site. You apply with them directly — we never stand between you and the employer.

What this role is

Intel seeks a lead analog circuit designer to architect high-speed SerDes components for next-generation optical interconnects in data centers, advancing their silicon photonics technology from 400G to 1.6T+ speeds. This role suits experienced mixed-signal IC designers comfortable guiding teams through complex analog CMOS blocks and collaborating across digital and physical design disciplines.

Our summary, not Intel’s wording. The full posting is on their site.

Skills this role names

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What they ask for

Required

  • MS in Electrical Engineering
  • 8+ years high-speed serial links experience
  • Deep sub-micron CMOS/BiCMOS design
  • Hands-on circuit design of SerDes blocks at 28Gbps+ data rates
  • Precision analog circuit design (ADC/DAC)
  • PAM4/NRZ link design
  • Full-chip design and verification experience

Nice to have

  • Optical communications familiarity
  • 400G/800G/1.6T optical link experience
  • Package and test setup design experience

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