# Very Large Scale Integration (VLSI)

Skill · Engineering (Mechanical, Electrical, Civil and Environmental)

Canonical page: https://career.thegoodapps.co/skills/very-large-scale-integration-vlsi

VLSI refers to the process of creating integrated circuits by combining millions or billions of transistors onto a single chip, forming the basis of modern microprocessors, memory chips, and other semiconductor devices. VLSI engineers design, simulate, and verify chip layouts using specialized tools and hardware description languages like Verilog or VHDL. It is a core discipline within electrical engineering and the semiconductor industry.

## Very Large Scale Integration (VLSI) in the job market

- Open roles: 10
- Employers hiring: 3
- Last checked: September 13, 2026

## Asked for alongside Very Large Scale Integration (VLSI)

Measured from the 10 open roles that name Very Large Scale Integration (VLSI), not from a curated list.

- [Python](https://career.thegoodapps.co/skills/python) — 6 roles (60.0%)
- [Unix](https://career.thegoodapps.co/skills/unix) — 4 roles (40.0%)
- [C++](https://career.thegoodapps.co/skills/c-2) — 3 roles (30.0%)

## Roles that use Very Large Scale Integration (VLSI)

- [Design Engineer](https://career.thegoodapps.co/occupations/design-engineer) — 1
- [Layout Designer](https://career.thegoodapps.co/occupations/layout-designer) — 1
- [Software Engineer](https://career.thegoodapps.co/occupations/software-engineer) — 1
- [Technical Program Manager](https://career.thegoodapps.co/occupations/technical-program-manager) — 1

Related skills: [Verilog](https://career.thegoodapps.co/skills/verilog), [VHDL](https://career.thegoodapps.co/skills/vhdl)

## Open roles requiring Very Large Scale Integration (VLSI) (10)

- [Senior Physical Design Interposer Engineer](https://career.thegoodapps.co/jobs/1764b41d-c622-47b5-b975-cf5c4b66e636/senior-physical-design-interposer-engineer-at-nvidia) at [NVIDIA](https://career.thegoodapps.co/organizations/nvidia) — $136,000 – $218,500
- [ICE Graduate Talent](https://career.thegoodapps.co/jobs/fe740c10-ee03-4679-ad6e-04cfd889520b/ice-graduate-talent-at-intel) at [Intel](https://career.thegoodapps.co/organizations/intel) — Contract
- [Design Engineer](https://career.thegoodapps.co/jobs/52a646f0-4184-4eeb-bdbd-d31f9a4c59ac/design-engineer-at-broadcom-inc) at [Broadcom Inc.](https://career.thegoodapps.co/organizations/broadcom-inc) — Full-time, Fort Collins, CO, $60,200 – $96,300
- [Senior Technical Program Manager – VLSI](https://career.thegoodapps.co/jobs/71ff8e75-d011-4437-b7f6-f1503bf4abe1/senior-technical-program-manager-vlsi-at-nvidia) at [NVIDIA](https://career.thegoodapps.co/organizations/nvidia) — Full-time, Santa Clara, CA, $168,000 – $322,000
- [CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG)](https://career.thegoodapps.co/jobs/7d172b71-c3f3-45ec-abeb-d2203572fb59/cpu-soc-mask-layout-designer-diploma-level-contract-role-silicon-engineering) at [Intel](https://career.thegoodapps.co/organizations/intel) — Contract
- [Senior Software Development Engineer, Neural Graph Infrastructure](https://career.thegoodapps.co/jobs/1a132e0c-a972-41cb-ac81-9953db8d1d44/senior-software-development-engineer-neural-graph-infrastructure-at-nvidia) at [NVIDIA](https://career.thegoodapps.co/organizations/nvidia) — Santa Clara, CA, $168,000 – $310,500
- [Graduate Talent (CPU-SoC Silicon Design)](https://career.thegoodapps.co/jobs/22dbd492-b32a-4022-a12d-00595c8076e5/graduate-talent-cpu-soc-silicon-design-at-intel) at [Intel](https://career.thegoodapps.co/organizations/intel) — Contract
- [Senior DFT Power Methodology Engineer](https://career.thegoodapps.co/jobs/94635d28-3bf7-481b-9c7f-827127d5bb0a/senior-dft-power-methodology-engineer-at-nvidia) at [NVIDIA](https://career.thegoodapps.co/organizations/nvidia) — Santa Clara, CA, $196,000 – $368,000
- [Senior USB IP Design Verification Engineer](https://career.thegoodapps.co/jobs/a1c708f2-8d37-4830-a87d-1d2bbbe7d626/senior-usb-ip-design-verification-engineer-at-intel) at [Intel](https://career.thegoodapps.co/organizations/intel) — Full-time
- [Senior Manager, ASIC Chip Engineering](https://career.thegoodapps.co/jobs/47905b36-5926-43b4-bcbe-2c66e1429d90/senior-manager-asic-chip-engineering-at-nvidia) at [NVIDIA](https://career.thegoodapps.co/organizations/nvidia) — Santa Clara, CA, $232,000 – $368,000