# Design For Test Engineer III (IC)

Hiring organization: [Arrow Electronics](https://career.thegoodapps.co/organizations/arrow-electronics)

Canonical page: https://career.thegoodapps.co/jobs/fc01b942-48b3-4e11-8e5d-e063a0e03aa3

Listed on Arrow Electronics's own careers site. Applications go to them directly.

- Employment type: full time
- Seniority: Senior
- Location: San Jose, CA
- Salary: 95900 – 170500 USD per year

## Summary

This role involves designing and implementing Design For Test solutions for advanced networking chips at 3nm and 5nm nodes, working with industry-standard tools like Tessent and Tetramax to develop test patterns, verify memory and JTAG functionality, and automate DFT flows through scripting. It suits experienced DFT engineers who have worked on complex SoCs and want to apply their expertise in semiconductor test methodology at a large global company.

_Our summary, not Arrow Electronics's wording._

## Skills named

Perl, Tcl

## Required

- 5–7 years of DFT experience
- Scan insertion and ATPG pattern generation
- Pattern simulation with and without timing
- MBIST insertion and verification
- IEEE 1149.1 JTAG insertion and verification
- Scripting in Perl, Shell, or TCL
- Experience on multi-million gate count SoCs
- Mentor Tessent experience
- B.Tech or M.Tech in Microelectronics or Electronics

## Nice to have

- Networking, Consumer, or IP block (PLL, Serdes) experience
- Low power DFT experience

Apply on Arrow Electronics's site: https://arrow.wd1.myworkdayjobs.com/en-US/AC/job/US-CA-San-Jose-California/Design-For-Test-Engineer-III--IC-_R246309-1