# Analog Layout Design Engineer

Hiring organization: [Intel](https://career.thegoodapps.co/organizations/intel)

Canonical page: https://career.thegoodapps.co/jobs/f76dfcf5-fcd9-4441-96b6-c7b5def16fdb

Listed on Intel's own careers site. Applications go to them directly.

- Employment type: full time
- Seniority: Mid
- Salary: 122440 – 172860 USD per year

## Summary

Intel is hiring an Analog Layout Design Engineer to create and optimize layouts for analog signal circuits in semiconductor designs. This role suits engineers with experience in analog device layout, Cadence tools, and CMOS technologies who want to work on cutting-edge chip design with cross-functional teams.

_Our summary, not Intel's wording._

## Required

- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 3+ years of experience, or Master's degree with 2+ years
- Analog device and metal layout fundamentals including analog/mixed-signal understanding
- Cadence Virtuoso Layout Suite and Calibre/ICV DRC proficiency
- CMOS technologies and high-voltage rules knowledge
- Floor planning and hierarchical layout planning for analog and mixed-signal blocks
- Layout performance verification and debug capabilities

## Nice to have

- Strong understanding of analog layout effects such as mismatch, parasitics, IR drop, and electromigration
- Application of common-centroid, interdigitation, and symmetry-based layout techniques
- Process variation and gradient effect evaluation and mitigation
- Parasitic-aware design using extraction and simulation tools
- Debugging layout issues by correlating LVS, DRC, extraction, and silicon behavior
- Noise isolation, shielding, and signal integrity optimization in mixed-signal environments

Apply on Intel's site: https://intel.wd1.myworkdayjobs.com/en-US/External/job/US-Oregon-Hillsboro/Analog-Layout-Design-Engineer_JR0285142