# Senior RTL Design Engineer

Hiring organization: [Baidu](https://career.thegoodapps.co/organizations/baidu)

Canonical page: https://career.thegoodapps.co/jobs/ead6df0a-8ad5-4886-a8f9-8f5a06f25dbd

Listed on Baidu's own careers site. Applications go to them directly.

- Seniority: Senior
- Location: Sunnyvale, CA

## Summary

This role involves designing and implementing CPU cores in RISC-V, working from microarchitecture through physical optimization. It suits experienced hardware engineers with a track record shipping processors and expertise in areas like caching, execution units, or memory subsystems.

_Our summary, not Baidu's wording._

## Skills named

Risc-V, Scala, SystemVerilog, Verilog, VHDL

## Required

- 8+ years of experience in high-performance CPU design
- Expertise in at least one CPU microarchitecture domain (fetch/decode, branch prediction, register renaming, execution units, load-store unit, cache, or memory subsystems)
- RTL design proficiency in Verilog, SystemVerilog, or VHDL
- Knowledge of at least one object-oriented or functional programming language
- Successful CPU development experience from architecture through tapeout
- MS or PhD in EE, CE, CS, or related field, or equivalent experience

## Nice to have

- RISC-V architecture knowledge
- Scala and/or Chisel experience

Apply on Baidu's site: https://job-boards.greenhouse.io/baidu/jobs/4499691