# Senior Physical Design and Timing Engineer

Hiring organization: [NVIDIA](https://career.thegoodapps.co/organizations/nvidia)

Canonical page: https://career.thegoodapps.co/jobs/e7fb27cc-4428-408b-b1a7-dbd9d771adc6

Listed on NVIDIA's own careers site. Applications go to them directly.

- Seniority: Senior
- Location: Westford, MA
- Salary: 168000 – 310500 USD per year

## Summary

Senior ASIC Timing Engineer role at NVIDIA focused on optimizing timing and physical design for high-frequency, low-power networking chips from synthesis through final layout. Suited for experienced engineers with deep expertise in static timing analysis, ECO implementation, and chip-level design optimization who want to contribute to industry-leading semiconductor products.

_Our summary, not NVIDIA's wording._

## Skills named

Make (Integromat), Python, Static Timing Analysis, Tcl

## Required

- BS in Electrical or Computer Engineering with 8 years experience, or MS with 4+ years in synthesis and timing
- Hands-on experience in full-chip/sub-chip static timing analysis and timing constraints management
- Expertise in fixing timing paths through ECOs including crosstalk and noise analysis
- Expertise in physical design optimization including placement, routing, cell sizing, buffering, and logic restructuring
- Background in logic synthesis or logical equivalence checking
- Deep knowledge of industry standard EDA tools like PrimeTime or Tempus
- Proficiency in Python, Tcl, and Make for automation

## Nice to have

- Domain-specific STA and timing convergence experience in CPUs, GPUs, network processors, or SOCs
- Understanding of DFT logic and DFT timing closure experience
- Knowledge of deep sub-micron technology and process variation effects
- Experience in methodology, flow development, or automation

Apply on NVIDIA's site: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-MA-Westford/Senior-ASIC-Timing-Engineer_JR2011363-1