# Senior Power Integrity Co-Design Engineer

Hiring organization: [NVIDIA](https://career.thegoodapps.co/organizations/nvidia)

Canonical page: https://career.thegoodapps.co/jobs/dec26424-55a6-466e-b149-f16a56f052c9

Listed on NVIDIA's own careers site. Applications go to them directly.

- Employment type: full time
- Seniority: Senior
- Location: Santa Clara, CA
- Salary: 136000 – 264500 USD per year

## Summary

Design and optimize voltage noise and power delivery across chip, package, and board for next-generation silicon, working across multiple teams to translate product targets into shipped specifications and drive show-stopper issues to closure.

_Our summary, not NVIDIA's wording._

## Skills named

Artificial Intelligence (AI), Machine Learning, Monte Carlo Simulation

## Required

- BS/MS/PhD in EE, CE, or related field or equivalent experience
- 5+ years in silicon power integrity, voltage noise, or PDN
- Deep expertise in at least one of: di/dt analysis and mitigation, voltage droop, PDN design, transient noise, or decap budgeting
- Hands-on silicon bringup, characterization, and correlation experience
- Strong simulation-to-silicon correlation skills
- System-level thinking and ability to make decisions across competing requirements
- Multi-functional collaboration in matrix environments
- Spec documentation rigor and closure discipline

## Nice to have

- Patents or publications in power integrity or related areas
- Experience with groundbreaking GPU, CPU, or AI accelerator silicon (Hopper/Blackwell class)
- ML/AI applied to noise modeling, transient prediction, or droop response
- Multi-rail, multi-domain PDN ownership at SoC level across die, package, and board
- Track record of codifying methodology into reusable workflows or tooling

Apply on NVIDIA's site: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Power-Integrity-Co-Design-Engineer_JR2018836-2