# Senior ASIC Design Engineer

Hiring organization: [NVIDIA](https://career.thegoodapps.co/organizations/nvidia)

Canonical page: https://career.thegoodapps.co/jobs/dd38a9c0-e334-4ce4-ac4f-423b0bb0a0cb

Listed on NVIDIA's own careers site. Applications go to them directly.

- Seniority: Senior
- Location: Santa Clara, CA
- Salary: 168000 – 310500 USD per year

## Summary

NVIDIA seeks a senior chip design engineer to architect and implement network-on-chip and interconnect components for their processors and GPUs, working across verification, synthesis, and physical design to deliver production-ready silicon.

_Our summary, not NVIDIA's wording._

## Skills named

Computer Architecture, SystemVerilog, Verilog

## Required

- Bachelor's or Master's degree in Electrical Engineering or Computer Engineering (or equivalent)
- 8+ years of RTL/build experience on complex interconnect or memory system units
- Proficiency in Verilog and/or SystemVerilog
- Deep understanding of ASIC flow including RTL, verification, synthesis, timing, ECO, and post-silicon debug
- Experience with arbiters, scheduling, synchronization, bus protocols, and interconnect networks

## Nice to have

- Familiarity with arbitration policies, interconnection routing, deadlock avoidance, and virtual channels
- Strong debugging and analytical skills

Apply on NVIDIA's site: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer_JR2011971