# ASIC Design Verification Engineer

Hiring organization: [Broadcom Inc.](https://career.thegoodapps.co/organizations/broadcom-inc)

Canonical page: https://career.thegoodapps.co/jobs/d743d432-134f-4c24-b509-860afbb68965

Listed on Broadcom Inc.'s own careers site. Applications go to them directly.

- Employment type: full time
- Seniority: Senior
- Salary: 129400 – 207000 USD per year

## Summary

This role involves developing comprehensive verification testbenches for high-performance Ethernet ASICs used in cloud and AI/ML applications, using constrained random methodologies to ensure design correctness. You'll work with senior engineers across design and architecture teams to verify complex silicon that pushes the boundaries of throughput and power efficiency.

_Our summary, not Broadcom Inc.'s wording._

## Skills named

Object-Oriented Programming (OOP), Perl, Python, SystemVerilog

## Required

- 12+ years experience in design verification (or 10+ with Masters, or 3+ with PhD)
- Constrained random verification methodologies
- Coverage-driven closure experience
- SystemVerilog testbench development
- UVM framework experience

## Nice to have

- Python or Perl scripting
- Advanced SystemVerilog features (assertions, classes)
- Deep OOP understanding

Apply on Broadcom Inc.'s site: https://broadcom.wd1.myworkdayjobs.com/en-US/External_Career/job/USA-CA-Irvine-Alton-Parkway-Bldg-2/ASIC-Design-Verification-Engineer_R026277