# Senior ASIC Design Engineer - DFX

Hiring organization: [NVIDIA](https://career.thegoodapps.co/organizations/nvidia)

Canonical page: https://career.thegoodapps.co/jobs/c6a4d6b8-50be-429c-874f-cdced871daaf

Listed on NVIDIA's own careers site. Applications go to them directly.

- Seniority: Senior
- Location: Santa Clara, CA
- Salary: 168000 – 310500 USD per year

## Summary

NVIDIA is hiring a senior engineer to architect and implement design-for-test solutions for their next-generation AI chips, working across the full silicon lifecycle from design through post-silicon validation. This role suits someone with deep DFT expertise and SoC design experience who enjoys mentoring others and collaborating across hardware and software teams.

_Our summary, not NVIDIA's wording._

## Skills named

Perl, Python, Static Timing Analysis, Tcl, Verilog

## Required

- Bachelor's degree in Electrical Engineering or equivalent experience, with 8+ years total experience (or Master's degree with 6+ years)
- 5+ years hands-on SoC architecture, RTL design, and verification
- Proficiency in Verilog and micro-architecture
- Deep expertise in DFT design, methodology, and implementation
- Experience with post-silicon bring-up on ATE
- Scripting proficiency in Python, Perl, or Tcl
- Strong communication and collaborative skills

## Nice to have

- UVM experience
- Familiarity with clocking, STA, place & route, and power optimization

Apply on NVIDIA's site: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer---DFX_JR2020883