# Senior ASIC Design Engineer – Clocks IP

Hiring organization: [NVIDIA](https://career.thegoodapps.co/organizations/nvidia)

Canonical page: https://career.thegoodapps.co/jobs/bd1dbe7b-5ea4-4243-b91b-95f0d8a35643

Listed on NVIDIA's own careers site. Applications go to them directly.

- Employment type: full time
- Seniority: Senior
- Salary: 136000 – 218500 USD per year

## Summary

This role designs the clock distribution networks for NVIDIA's GPUs and CPUs, working across multiple teams to balance power, performance, and area while managing the physical implementation and silicon validation of high-speed clocking solutions. It suits engineers with strong RTL design and logic optimization experience who want to influence chip architecture at a fundamental level.

_Our summary, not NVIDIA's wording._

## Skills named

Python, Verilog

## Required

- BS in Electrical Engineering or equivalent experience
- 3+ years of relevant work experience
- Deep understanding of logic optimization and PPA trade-offs
- Experience in RTL design (Verilog), verification and logic synthesis
- Strong coding skills in Python or other industry-standard scripting languages
- Ability to collaborate across multiple teams

## Nice to have

- MS in Electrical Engineering
- Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects
- Experience implementing on-chip clocking networks
- Experience with clocks controller and clocks logic design
- Understanding of system-level artifacts like power and noise
- Experience with scalable designs and architecture
- Hands-on silicon debug experience

Apply on NVIDIA's site: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer---Clocks-IP_JR2022532